mlsanityData to 7 Oct 2026

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

arXiv 2305.13243 ↗First posted 22 May 2023cs.LG cs.AR cs.PLcited by 136

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Abstract (arXiv)

Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially-available instruction-tuned Large Language Models (LLMs) such as OpenAI's ChatGPT and Google's Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Given that these `conversational' LLMs perform best when used interactively, we perform a case study where a hardware engineer co-architects a novel 8-bit accumulator-based microprocessor architecture with the LLM according to real-world hardware constraints. We then sent the processor to tapeout in a Skywater 130nm shuttle, meaning that this `Chip-Chat' resulted in what we believe to be the world's first wholly-AI-written HDL for tapeout.

Key facts. Cited by 136 papers in the map (data through 7 Oct 2026). Builds on 14 of its 33 references that are in the map. First posted on arXiv 22 May 2023.

Builds on

14 of 33 references.

References · 14

  1. 2017Attention Is All You Needcited by 59,932
  2. 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,204
  3. 2020Language Models are Few-Shot Learnerscited by 32,199
  4. 2022Training language models to follow instructions with human feedbackcited by 15,712
  5. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  6. 2022Self-Instruct: Aligning Language Models with Self-Generated Instructionscited by 2,674
  7. 2021Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributionscited by 417
  8. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
  9. 2021Examining Zero-Shot Vulnerability Repair with Large Language Modelscited by 105
  10. 2021Machine Learning for Electronic Design Automation: A Surveycited by 71
  11. 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
  12. 2023Towards Human-Bot Collaborative Software Architecting with ChatGPTcited by 31
2 more
  1. 2018Developing Synthesis Flows Without Human Knowledgecited by 29
  2. 2022Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Designcited by 3

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2023: 12; 2024: 45; 2025: 48; 2026: 31.

136 papers.

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  1. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  3. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  4. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  5. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  6. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  7. 2023Algorithm Evolution Using Large Language Modelcited by 52
  8. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
  9. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  10. 2024ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Modelscited by 44
  11. 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 42
  12. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
38 more
  1. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  2. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  3. 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 35
  4. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
  5. 2023Large Language Model for Multi-objective Evolutionary Optimizationcited by 29
  6. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
  7. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  8. 2024AMSNet: Netlist Dataset for AMS Circuitscited by 24
  9. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
  10. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  11. 2023LLM for SoC Security: A Paradigm Shiftcited by 22
  12. 2023LLM4DV: Using Large Language Models for Hardware Test Stimuli Generationcited by 21
  13. 2024CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generationcited by 19
  14. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  15. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
  16. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  17. 2024AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Modelscited by 17
  18. 2025SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoningcited by 16
  19. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  20. 2024A Multi-Expert Large Language Model Architecture for Verilog Code Generationcited by 15
  21. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
  22. 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
  23. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 14
  24. 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuitscited by 14
  25. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  26. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
  27. 2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
  28. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  29. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  30. 2024All Artificial, Less Intelligence: GenAI through the Lens of Formal Verificationcited by 11
  31. 2024LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generationcited by 11
  32. 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
  33. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  34. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 10
  35. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
  36. 2025DeepRTL2: A Versatile Model for RTL-Related Taskscited by 10
  37. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  38. 2024FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardwarecited by 9

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