mlsanityData to 14 Oct 2026

PyraNet: A Multi-Layered Hierarchical Dataset for Verilog

arXiv 2412.06947 ↗First posted 9 Dec 2024cs.AR cs.AI cs.LGcited by 19

Not on the map. Why?

Abstract (arXiv)

Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated Verilog code remains suboptimal. This is largely due to the absence of well-defined, well-organized datasets with high-quality samples, as well as a lack of innovative fine-tuning methods and models specifically trained on Verilog. In this paper, we introduce a novel open-source dataset and a corresponding fine-tuning technique, which utilizes a multi-layered structure that we refer to as PyraNet. Our experiments demonstrate that employing the proposed dataset and fine-tuning approach leads to a more accurate fine-tuned model, producing syntactically and functionally correct Verilog code. The evaluation results show improvements by up-to 32.6% in comparison to the CodeLlama-7B baseline model and up-to 16.7% in comparison to the state-of-the-art models using VerilogEval evaluation platform.

Key facts. Cited by 19 papers in the map (data through 14 Oct 2026). Builds on 17 of its 29 references that are in the map. First posted on arXiv 9 Dec 2024.

Builds on

17 of 29 references.

References · 17

  1. 2017Attention Is All You Needcited by 60,361
  2. 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,399
  3. 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,380
  4. 2022LaMDA: Language Models for Dialog Applicationscited by 1,220
  5. 2016Hyperband: A Novel Bandit-Based Approach to Hyperparameter Optimizationcited by 699
  6. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  7. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  8. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  9. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  10. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  11. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  12. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
5 more
  1. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  2. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  3. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  4. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  5. 2024A Multi-Expert Large Language Model Architecture for Verilog Code Generationcited by 15

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 10; 2026: 9.

19 papers.

Sort:

By area:

  1. 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
  2. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  3. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  4. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  5. 2026ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Designcited by 8
  6. 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
  7. 2026Forgetting in Language Models: Capacity, Optimization, and Self-Generated Replaycited by 7
  8. 2025TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generationcited by 4
  9. 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generationcited by 4
  10. 2025VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Promptscited by 2
  11. 2025Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligencecited by 1
  12. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
7 more
  1. 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
  2. 2026TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilogcited by 1
  3. 2025VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learningcited by 0
  4. 2026AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designscited by 0
  5. 2026Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automationcited by 0
  6. 2026OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Designcited by 0
  7. 2026LLM4RTL: Tool-Assisted LLM for RTL Generationcited by 0