mlsanityData to 7 Oct 2026

AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning

arXiv 2604.18445 ↗First posted 20 Apr 2026cs.LG cs.ARcited by 0

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Abstract (arXiv)

Performance, power, and area (PPA) optimization is a fundamental task in RTL design, requiring a precise understanding of circuit functionality and the relationship between circuit structures and PPA metrics. Recent studies attempt to automate this process using LLMs, but neither feedback-based nor knowledge-based methods are efficient enough, as they either design without any prior knowledge or rely heavily on human-summarized optimization rules. In this paper, we propose AutoPPA, a fully automated PPA optimization framework. The key idea is to automatically generate optimization rules that enhance the search for optimal solutions. To do this, AutoPPA employs an Explore-Evaluate-Induce (E2I) workflow that contrasts and abstracts rules from diverse generated code pairs rather than manually defined prior knowledge, yielding better optimization patterns. To make the abstracted rules more generalizable, AutoPPA employs an adaptive multi-step search framework that adopts the most effective rules for a given circuit. Experiments show that AutoPPA outperforms both the manual optimization and the state-of-the-art methods SymRTLO and RTLRewriter.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 20 of its 30 references that are in the map. First posted on arXiv 20 Apr 2026.

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References · 20

  1. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  2. 2023Reflexion: Language Agents with Verbal Reinforcement Learningcited by 4,064
  3. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  4. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  5. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  6. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  7. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  8. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  9. 2021Machine Learning for Electronic Design Automation: A Surveycited by 71
  10. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 69
  11. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  12. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
8 more
  1. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  2. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  3. 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generationcited by 34
  4. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
  5. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 30
  6. 2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineerscited by 24
  7. 2025SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoningcited by 16
  8. 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14

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