Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework
Not on the map. Why?
Abstract (arXiv)
The reproduction of hardware architectures from academic papers remains a significant challenge due to the lack of publicly available source code and the complexity of hardware description languages (HDLs). To this end, we propose ArchCraft, a Framework that converts abstract architectural descriptions from academic papers into synthesizable Verilog projects with register-transfer level (RTL) verification. ArchCraft introduces a structured workflow, which uses formal graphs to capture the Architectural Blueprint and symbols to define the Functional Specification, translating unstructured academic papers into verifiable, hardware-aware designs. The framework then generates RTL and testbench (TB) code decoupled via these symbols to facilitate verification and debugging, ultimately reporting the circuit's Power, Area, and Performance (PPA). Moreover, we propose the first benchmark, ArchSynthBench, for synthesizing hardware from architectural descriptions, with a complete set of evaluation indicators, 50 project-level circuits, and around 600 circuit blocks. We systematically assess ArchCraft on ArchSynthBench, where the experiment results demonstrate the superiority of our proposed method, surpassing direct generation methods and the VerilogCoder framework in both paper understanding and code completion. Furthermore, evaluation and physical implementation of the generated executable RTL code show that these implementations meet all timing constraints without violations, and their performance metrics are consistent with those reported in the original papers.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 35 of its 75 references that are in the map. First posted on arXiv 8 Nov 2025.
Builds on
35 of 75 references.
References · 35
- 2024A Survey on LLM-as-a-Judgecited by 1,423
- 2025Agent Laboratory: Using LLM Agents as Research Assistantscited by 425
- 2024MLLM-as-a-Judge: Assessing Multimodal LLM-as-a-Judge with Vision-Language Benchmarkcited by 372
- 2023RepoCoder: Repository-Level Code Completion Through Iterative Retrieval and Generationcited by 367
- 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
- 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
- 2025ChartCoder: Advancing Multimodal Large Language Model for Chart-to-Code Generationcited by 92
- 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
- 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
- 2025AutoReproduce: Automatic AI Experiment Reproduction with Paper Lineagecited by 32
- 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
23 more
- 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
- 2025PIM Is All You Need: A CXL-Enabled GPU-Free System for Large Language Model Inferencecited by 22
- 2025VinciCoder: Unifying Multimodal Code Generation via Coarse-to-fine Visual Reinforcement Learningcited by 21
- 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
- 2024LUT Tensor Core: A Software-Hardware Co-Design for LUT-Based Low-Bit LLM Inferencecited by 18
- 2024Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloadscited by 15
- 2025TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Treescited by 15
- 2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
- 2024PolyLUT-Add: FPGA-based LUT Inference with Wide Inputscited by 12
- 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metriccited by 12
- 2023A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edgecited by 11
- 2025DeepRTL2: A Versatile Model for RTL-Related Taskscited by 10
- 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
- 2025RTLSquad: Multi-Agent Based Interpretable RTL Designcited by 9
- 2024ReducedLUT: Table Decomposition with "Don't Care" Conditionscited by 7
- 2024A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Trainingcited by 6
- 2025TENET: An Efficient Sparsity-Aware LUT-Centric Architecture for Ternary LLM Inference On Edgecited by 6
- 2024Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsitycited by 5
- 2024H2PIPE: High throughput CNN Inference on FPGAs with High-Bandwidth Memorycited by 3
- 2025BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Accelerationcited by 3
- 2023AutoWS: Automate Weights Streaming in Layer-wise Pipelined DNN Acceleratorscited by 2
- 2024A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELUcited by 2
- 2022COMPAQT: Compressed Waveform Memory Architecture for Scalable Qubit Controlcited by 1
Built on by
Citing papers per year: 2026: 1.
1 paper.