mlsanityData to 14 Oct 2026

DeepRTL2: A Versatile Model for RTL-Related Tasks

arXiv 2506.15697 ↗First posted 28 May 2025cs.AR cs.CL cs.LGcited by 10

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Abstract (arXiv)

The integration of large language models (LLMs) into electronic design automation (EDA) has significantly advanced the field, offering transformative benefits, particularly in register transfer level (RTL) code generation and understanding. While previous studies have demonstrated the efficacy of fine-tuning LLMs for these generation-based tasks, embedding-based tasks, which are equally critical to EDA workflows, have been largely overlooked. These tasks, including natural language code search, RTL code functionality equivalence checking, and performance prediction, are essential for accelerating and optimizing the hardware design process. To address this gap, we present DeepRTL2, a family of versatile LLMs that unifies both generation- and embedding-based tasks related to RTL. By simultaneously tackling a broad range of tasks, DeepRTL2 represents the first model to provide a comprehensive solution to the diverse challenges in EDA. Through extensive experiments, we show that DeepRTL2 achieves state-of-the-art performance across all evaluated tasks.

Key facts. Cited by 10 papers in the map (data through 14 Oct 2026). Builds on 21 of its 40 references that are in the map. First posted on arXiv 28 May 2025.

Builds on

21 of 40 references.

References · 21

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9 more
  1. 2022SGPT: GPT Sentence Embeddings for Semantic Searchcited by 204
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  3. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
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  6. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  7. 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
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Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 5; 2026: 5.

10 papers.

  1. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  2. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  3. 2025Assessing Large Language Models in Generating RTL Design Specificationscited by 2
  4. 2026TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertioncited by 2
  5. 2025Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learningcited by 1
  6. 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
  7. 2026MHRC-Bench: A Multilingual Hardware Repository-Level Code Completion benchmarkcited by 1
  8. 2026QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generationcited by 1
  9. 2026UniRTL: Unifying Code and Graph for Robust RTL Representation Learningcited by 0
  10. 2026RTLCurator: Label-Efficient Data Curation for RTL Generationcited by 0