mlsanityData to 7 Oct 2026

SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning

arXiv 2504.10369 ↗First posted 14 Apr 2025cs.AR cs.AI cs.LGcited by 16

On the map: LLM reasoning → Reasoning for agents, planning and code

Abstract (arXiv)

Optimizing Register Transfer Level (RTL) code is crucial for improving the power, performance, and area (PPA) of digital circuits in the early stages of synthesis. Manual rewriting, guided by synthesis feedback, can yield high-quality results but is time-consuming and error-prone. Most existing compiler-based approaches have difficulty handling complex design constraints. Large Language Model (LLM)-based methods have emerged as a promising alternative to address these challenges. However, LLM-based approaches often face difficulties in ensuring alignment between the generated code and the provided prompts. This paper presents SymRTLO, a novel neuron-symbolic RTL optimization framework that seamlessly integrates LLM-based code rewriting with symbolic reasoning techniques. Our method incorporates a retrieval-augmented generation (RAG) system of optimization rules and Abstract Syntax Tree (AST)-based templates, enabling LLM-based rewriting that maintains syntactic correctness while minimizing undesired circuit behaviors. A symbolic module is proposed for analyzing and optimizing finite state machine (FSM) logic, allowing fine-grained state merging and partial specification handling beyond the scope of pattern-based compilers. Furthermore, a fast verification pipeline, combining formal equivalence checks with test-driven validation, further reduces the complexity of verification. Experiments on the RTL-Rewriter benchmark with Synopsys Design Compiler and Yosys show that SymRTLO improves power, performance, and area (PPA) by up to 43.9%, 62.5%, and 51.1%, respectively, compared to the state-of-the-art methods.

Key facts. Cited by 16 papers in the map (data through 7 Oct 2026). Placed in Reasoning for agents, planning and code, one of 17 directions in LLM reasoning. Builds on 15 of its 50 references that are in the map. First posted on arXiv 14 Apr 2025.

Builds on

15 of 50 references.

References · 15

  1. 2023GPT-4 Technical Reportcited by 18,132
  2. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  3. 2023A Comprehensive Capability Analysis of GPT-3 and GPT-3.5 Series Modelscited by 244
  4. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  5. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  6. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  7. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  8. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  9. 2024Logically Consistent Language Models via Neuro-Symbolic Integrationcited by 30
  10. 2023MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Designcited by 19
  11. 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
  12. 2024PyOD 2: A Python Library for Outlier Detection with LLM-powered Model Selectioncited by 17
3 more
  1. 2023Code Prompting: a Neural Symbolic Method for Complex Reasoning in Large Language Modelscited by 16
  2. 2024Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecturecited by 7
  3. 2024Neurosymbolic AI approach to Attribution in Large Language Modelscited by 3

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 5; 2026: 11.

16 papers.

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  1. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  2. 2025Autocomp: A Powerful and Portable Code Optimizer for Tensor Acceleratorscited by 12
  3. 2026POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimizationcited by 11
  4. 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
  5. 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
  6. 2025ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learningcited by 5
  7. 2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvementcited by 5
  8. 2026COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generationcited by 3
  9. 2025Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosiscited by 1
  10. 2026Trident : How to Break Deep Reinforcement Learning Cyber Defenses (Agentic)cited by 1
  11. 2026The New Compiler Stack: A Survey on the Synergy of LLMs and Compilerscited by 0
  12. 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learningcited by 0
4 more
  1. 2026Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generationcited by 0
  2. 2026AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewritingcited by 0
  3. 2026EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysiscited by 0
  4. 2026TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agentscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization
  2. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  3. 2026StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis
  4. 2026LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation
  5. 2026LongRTL: Graph-Similarity-Guided LLM-driven Long Context RTL Optimization ↗
  6. 2025Understanding and Mitigating Errors of LLM-Generated RTL Code
  7. 2026ReaComp: Compiling LLM Reasoning into Symbolic Solvers for Efficient Program Synthesis
  8. 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs