mlsanityData to 7 Oct 2026

DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base

arXiv 2510.05327 ↗First posted 6 Oct 2025cs.AR cs.AIcited by 1

On the map: Retrieval-augmented generation → RAG for code

Abstract (arXiv)

As large language models (LLMs) continue to be integrated into modern technology, there has been an increased push towards code generation applications, which also naturally extends to hardware design automation. LLM-based solutions for register transfer level (RTL) code generation for intellectual property (IP) designs have grown, especially with fine-tuned LLMs, prompt engineering, and agentic approaches becoming popular in literature. However, a gap has been exposed in these techniques, as they fail to integrate novel IPs into the model's knowledge base, subsequently resulting in poorly generated code. Additionally, as general-purpose LLMs continue to improve, fine-tuned methods on older models will not be able to compete to produce more accurate and efficient designs. Although some retrieval augmented generation (RAG) techniques exist to mitigate challenges presented in fine-tuning approaches, works tend to leverage low-quality codebases, incorporate computationally expensive fine-tuning in the frameworks, or do not use RAG directly in the RTL generation step. In this work, we introduce DeepV: a model-agnostic RAG framework to generate RTL designs by enhancing context through a large, high-quality dataset without any RTL-specific training. Our framework benefits the latest commercial LLM, OpenAI's GPT-5, with a near 17% increase in performance on the VerilogEval benchmark. We host DeepV for use by the community in a Hugging Face (HF) Space: https://huggingface.co/spaces/FICS-LLM/DeepV.

Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Placed in RAG for code, one of 15 directions in Retrieval-augmented generation. Builds on 47 of its 63 references that are in the map. First posted on arXiv 6 Oct 2025.

Builds on

47 of 63 references.

Closest ancestors · 1

Same direction, newest first

  1. 2025RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation11 Apr

Other references · 46

  1. 2019Sentence-BERT: Sentence Embeddings using Siamese BERT-Networkscited by 9,049
  2. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  3. 2017Billion-scale similarity search with GPUscited by 2,477
  4. 2023Retrieval-Augmented Generation for Large Language Models: A Surveycited by 2,185
  5. 2023Code Llama: Open Foundation Models for Codecited by 2,105
  6. 2022Competition-Level Code Generation with AlphaCodecited by 1,427
  7. 2022Least-to-Most Prompting Enables Complex Reasoning in Large Language Modelscited by 1,397
  8. 2020CodeBERT: A Pre-Trained Model for Programming and Natural Languagescited by 1,286
  9. 2024Parameter-Efficient Fine-Tuning for Large Models: A Comprehensive Surveycited by 641
  10. 2024A Systematic Survey of Prompt Engineering in Large Language Models: Techniques and Applicationscited by 428
  11. 2024The Faiss librarycited by 370
  12. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
34 more
  1. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  2. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  3. 2025AI Agents vs. Agentic AI: A Conceptual Taxonomy, Applications and Challengescited by 167
  4. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  5. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  6. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  7. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  8. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  9. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  10. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 69
  11. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
  12. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  13. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
  14. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  15. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 41
  16. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 41
  17. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  18. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 38
  19. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  20. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  21. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 30
  22. 2023LLM for SoC Security: A Paradigm Shiftcited by 22
  23. 2023LLM4DV: Using Large Language Models for Hardware Test Stimuli Generationcited by 21
  24. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  25. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  26. 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
  27. 2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
  28. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  29. 2025VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistencycited by 11
  30. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  31. 2024CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generationcited by 9
  32. 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generationcited by 8
  33. 2025ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verificationcited by 7
  34. 2025SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Designcited by 4

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2026: 1.

1 paper.

  1. 2026Evidence-Driven LLM Agent for C-to-Synthesizable-C Conversion and Verificationcited by 1

Similar, not cited

Close in wording, no citation either way

  1. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
  2. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
  3. 2025Understanding and Mitigating Errors of LLM-Generated RTL Code
  4. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  5. 2024EDA-Aware RTL Generation with Large Language Models
  6. 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
  7. 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs
  8. 2026VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs