ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generation
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Abstract (arXiv)
Recently, large language models (LLMs) have demonstrated excellent performance, inspiring researchers to explore their use in automating register transfer level (RTL) code generation and improving hardware design efficiency. However, the existing approaches to fine-tune LLMs for RTL generation typically are conducted on fixed datasets, which do not fully stimulate the capability of LLMs and require large amounts of reference data, which are costly to acquire. To mitigate these issues, we innovatively introduce an iterative training paradigm named ITERTL. During each iteration, samples are drawn from the model trained in the previous cycle. Then these new samples are employed for training in current loop. Furthermore, we introduce a plug-and-play data filtering strategy, thereby encouraging the model to generate high-quality, self-contained code. Our model outperforms GPT4 and state-of-the-art (SOTA) open-source models, achieving remarkable 53.8% pass@1 rate on VerilogEval-human benchmark. Under similar conditions of data quantity and quality, our approach significantly outperforms the baseline. Extensive experiments validate the effectiveness of the proposed method.
Key facts. Cited by 9 papers in the map (data through 14 Oct 2026). Builds on 19 of its 28 references that are in the map. First posted on arXiv 28 Jun 2024.
Builds on
19 of 28 references.
References · 19
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7 more
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Citing papers per year: 2024: 1; 2025: 6; 2026: 2.
9 papers.
- 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
- 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generationcited by 8
- 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
- 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
- 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
- 2026EstRTL: Functional Estimation Guided RTL Code Generationcited by 0
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2026EstRTL: Functional Estimation Guided RTL Code Generation1 Jun 2026
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework8 Nov 2025
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead29 Oct 2025
- 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation22 Oct 2025
- 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base6 Oct 2025
- 2025Understanding and Mitigating Errors of LLM-Generated RTL Code7 Aug 2025
- 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation9 Jul 2025
- 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generation10 Dec 2024