Automated Generation of Microfluidic Netlists using Large Language Models
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Abstract (arXiv)
Microfluidic devices have emerged as powerful tools in various laboratory applications, but the complexity of their design limits accessibility for many practitioners. While progress has been made in microfluidic design automation (MFDA), a practical and intuitive solution is still needed to connect microfluidic practitioners with MFDA techniques. This work introduces the first practical application of large language models (LLMs) in this context, providing a preliminary demonstration. Building on prior research in hardware description language (HDL) code generation with LLMs, we propose an initial methodology to convert natural language microfluidic device specifications into system-level structural Verilog netlists. We demonstrate the feasibility of our approach by generating structural netlists for practical benchmarks representative of typical microfluidic designs with correct functional flow and an average syntactical accuracy of 88%.
Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 6 of its 17 references that are in the map. First posted on arXiv 22 Feb 2026.
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6 of 17 references.
References · 6
- 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 876
- 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
- 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
- 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
- 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
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