COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation
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Abstract (arXiv)
LLM-based RTL code generation methods increasingly target both functional correctness and PPA quality, yet existing approaches universally decouple the two objectives, optimizing PPA only after correctness is fully achieved. Whether through sequential multi-agent pipelines, evolutionary search with binary correctness gates, or hierarchical reward dependencies, partially correct but architecturally promising candidates are systematically discarded. Moreover, existing methods reduce the multi-objective PPA space to a single scalar fitness, obscuring the trade-offs among area, delay, and power. To address these limitations, we propose COEVO, a co-evolutionary framework that unifies correctness and PPA optimization within a single evolutionary loop. COEVO formulates correctness as a continuous co-optimization dimension alongside area, delay, and power, enabled by an enhanced testbench that provides fine-grained scoring and detailed diagnostic feedback. An adaptive correctness gate with annealing allows PPA-promising but partially correct candidates to guide the search toward jointly optimal solutions. To preserve the full PPA trade-off structure, COEVO employs four-dimensional Pareto-based non-dominated sorting with configurable intra-level sorting, replacing scalar fitness without manual weight tuning. Evaluated on VerilogEval 2.0 and RTLLM 2.0, COEVO achieves 97.5% and 94.5% Pass@1 with GPT-5.4-mini, surpassing all agentic baselines across four LLM backbones, while attaining the best PPA on 43 out of 49 synthesizable RTLLM designs.
Key facts. Cited by 3 papers in the map (data through 13 Oct 2026). Builds on 22 of its 41 references that are in the map. First posted on arXiv 16 Apr 2026.
Builds on
22 of 41 references.
References · 22
- 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
- 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
- 2023ChipGPT: How far are we from natural language hardware designcited by 105
- 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
- 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
- 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
- 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
- 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generationcited by 35
- 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
- 2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineerscited by 25
- 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
10 more
- 2025VFlow: Discovering Optimal Agentic Workflows for Verilog Generationcited by 19
- 2025SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoningcited by 16
- 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
- 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
- 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMscited by 12
- 2026POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimizationcited by 11
- 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
- 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
- 2026HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalationcited by 4
- 2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generationcited by 3
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Citing papers per year: 2026: 3.
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- 2026VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generation
- 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generation
- 2026StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis
- 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization
- 2024EDA-Aware RTL Generation with Large Language Models
- 2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
- 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
- 2026SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization