mlsanityData to 14 Oct 2026

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model

arXiv 2504.14560 ↗First posted 20 Apr 2025cs.AR cs.AIcited by 12

On the map: LLM reasoning → Reasoning for agents, planning and code

Abstract (arXiv)

Large Language Models (LLMs) have advanced Verilog code generation significantly, yet face challenges in data quality, reasoning capabilities, and computational efficiency. This paper presents ReasoningV, a novel model employing a hybrid reasoning strategy that integrates trained intrinsic capabilities with dynamic inference adaptation for Verilog code generation. Our framework introduces three complementary innovations: (1) ReasoningV-5K, a high-quality dataset of 5,000 functionally verified instances with reasoning paths created through multi-dimensional filtering of PyraNet samples; (2) a two-stage training approach combining parameter-efficient fine-tuning for foundational knowledge with full-parameter optimization for enhanced reasoning; and (3) an adaptive reasoning mechanism that dynamically adjusts reasoning depth based on problem complexity, reducing token consumption by up to 75% while preserving performance. Experimental results demonstrate ReasoningV's effectiveness with a pass@1 accuracy of 57.8% on VerilogEval-human, achieving performance competitive with leading commercial models like Gemini-2.0-flash (59.5%) and exceeding the previous best open-source model by 10.4 percentage points. ReasoningV offers a more reliable and accessible pathway for advancing AI-driven hardware design automation, with our model, data, and code available at https://github.com/BUAA-CLab/ReasoningV.

Key facts. Cited by 12 papers in the map (data through 14 Oct 2026). Placed in Reasoning for agents, planning and code, one of 17 directions in LLM reasoning. Builds on 31 of its 38 references that are in the map. First posted on arXiv 20 Apr 2025.

Builds on

31 of 38 references.

Closest ancestors · 1

Same direction, newest first

  1. 2025KodCode: A Diverse, Challenging, and Verifiable Synthetic Dataset for Coding4 Mar

Other references · 30

  1. 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,380
  2. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  3. 2025DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learningcited by 6,330
  4. 2023Qwen Technical Reportcited by 3,344
  5. 2025s1: Simple test-time scalingcited by 1,341
  6. 2025Stop Overthinking: A Survey on Efficient Reasoning for Large Language Modelscited by 464
  7. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  8. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  9. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  10. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  11. 2025A Survey of Efficient Reasoning for Large Reasoning Models: Language, Multimodality, and Beyondcited by 132
  12. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
18 more
  1. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  2. 2024A Comparative Study on Reasoning Patterns of OpenAI's o1 Modelcited by 63
  3. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  4. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  5. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  6. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  7. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  8. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 31
  9. 2021OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesiscited by 30
  10. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 26
  11. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  12. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  13. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  14. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
  15. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metriccited by 12
  16. 2025Paradigm-Based Automatic HDL Code Generation Using LLMscited by 6
  17. 2025Dynamic LLM Routing and Selection based on User Preferences: Balancing Performance, Cost, and Ethicscited by 6
  18. 2023Towards the Imagenets of ML4EDAcited by 1

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 10; 2026: 2.

12 papers.

  1. 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generationcited by 35
  2. 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
  3. 2025From Code Foundation Models to Agents and Applications: A Comprehensive Survey and Practical Guide to Code Intelligencecited by 15
  4. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  5. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  6. 2025ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learningcited by 5
  7. 2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Modelscited by 4
  8. 2025VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Promptscited by 2
  9. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
  10. 2025QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Designcited by 1
  11. 2026LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflowcited by 1
  12. 2026Benchmarking LLMs for Verilog Design Flowscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
  2. 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation
  3. 2026Tandem: Riding Together with Large and Small Language Models for Efficient Reasoning
  4. 2025Increasing LLM Coding Capabilities through Diverse Synthetic Coding Tasks
  5. 2026VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
  6. 2026Beyond Output Correctness: Benchmarking and Evaluating Large Language Model Reasoning in Coding Tasks
  7. 2025Speculative Decoding for Verilog: Speed and Quality, All in One
  8. 2026ORACLE: Optimizing Reasoning Abilities of Large Language Models via Constraint-Led Synthetic Data Elicitation