mlsanityData to 7 Oct 2026

AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies

arXiv 2503.00205 ↗First posted 28 Feb 2025cs.LG cs.ARcited by 35

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Abstract (arXiv)

The massive and large-scale design of foundational semiconductor integrated circuits (ICs) is crucial to sustaining the advancement of many emerging and future technologies, such as generative AI, 5G/6G, and quantum computing. Excitingly, recent studies have shown the great capabilities of foundational models in expediting the design of digital ICs. Yet, applying generative AI techniques to accelerate the design of analog ICs remains a significant challenge due to critical domain-specific issues, such as the lack of a comprehensive dataset and effective representation methods for analog circuits. This paper proposes, AnalogGenie, a underlineGeneratunderlineive underlineengine for automatic design/discovery of underlineAnalog circuit topologies--the most challenging and creative task in the conventional manual design flow of analog ICs. AnalogGenie addresses two key gaps in the field: building a foundational comprehensive dataset of analog circuit topology and developing a scalable sequence-based graph representation universal to analog circuits. Experimental results show the remarkable generation performance of AnalogGenie in broadening the variety of analog ICs, increasing the number of devices within a single design, and discovering unseen circuit topologies far beyond any prior arts. Our work paves the way to transform the longstanding time-consuming manual design flow of analog ICs to an automatic and massive manner powered by generative AI. Our source code is available at https://github.com/xz-group/AnalogGenie.

Key facts. Cited by 35 papers in the map (data through 7 Oct 2026). Builds on 18 of its 34 references that are in the map. First posted on arXiv 28 Feb 2025.

Builds on

18 of 34 references.

References · 18

  1. 2023GPT-4 Technical Reportcited by 18,132
  2. 2018GraphRNN: Generating Realistic Graphs with Deep Auto-regressive Modelscited by 406
  3. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  4. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  5. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  6. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  7. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
  8. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  9. 2020GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learningcited by 89
  10. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  11. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  12. 2022A Survey on Deep Graph Generation: Methods and Applicationscited by 69
6 more
  1. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
  2. 2023CktGNN: Circuit Graph Neural Network for Electronic Design Automationcited by 55
  3. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  4. 2024LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuitscited by 32
  5. 2022Domain Knowledge-Infused Deep Learning for Automated Analog/Radio-Frequency Circuit Parameter Optimizationcited by 10
  6. 2024RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization with Knowledge-infused Reinforcement Learningcited by 9

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 11; 2026: 24.

35 papers.

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  1. 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuitscited by 14
  2. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
  3. 2025AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizingcited by 10
  4. 2025AMSnet 2.0: A Large AMS Database with AI Segmentation for Net Detectioncited by 9
  5. 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimizationcited by 5
  6. 2025CircuitSense: A Hierarchical MLLM Benchmark Bridging Visual Comprehension and Symbolic Reasoning in Engineering Design Processcited by 3
  7. 2026Graph Tokenization for Bridging Graphs and Transformerscited by 3
  8. 2026AnalogAgent: Self-Improving Analog Circuit Design Automation with LLM Agentscited by 3
  9. 2025ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddingscited by 2
  10. 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generationcited by 2
  11. 2026CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Promptcited by 2
  12. 2025SPICEMixer - Netlist-Level Circuit Evolutioncited by 1
23 more
  1. 2026PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converterscited by 1
  2. 2026AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learningcited by 1
  3. 2026AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrievalcited by 1
  4. 2026RF-Agent: A Practical Framework for Building Language Agents for RFIC Designcited by 1
  5. 2026NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulationcited by 1
  6. 2025PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimizationcited by 0
  7. 2025AnalogFed: Privacy-Preserving Discovery of Analog Circuits at Scale with Federated Generative AIcited by 0
  8. 2025When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generationcited by 0
  9. 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSIIcited by 0
  10. 2026SchGen: PCB Schematic Generation with Semantic-Grounded Code Representationscited by 0
  11. 2026SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligencecited by 0
  12. 2026EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Modelscited by 0
  13. 2026ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuitscited by 0
  14. 2026Finding the Needle in a Haystack: Test-Time Analog Circuit Representation Adaptation for Bayesian Optimizationcited by 0
  15. 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Modelscited by 0
  16. 2026Spicing up Genetic Netlist Generation with LLMscited by 0
  17. 2026Analog-DB: An Agent-First Analog Integrated Circuit Database, From Blocks to Systemscited by 0
  18. 2026Circuit-MLLM: Topological Logic-Guided Latent-Space Visual Reasoning for Circuit Schematic Understandingcited by 0
  19. 2026Validation and Simulation Catch Different Errors: Four Levels of Evaluation for LLM-Generated Circuitscited by 0
  20. 2026Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Taskscited by 0
  21. 2026Inspector: Conversational and Lightweight Analyzer of Analog Circuit Layouts Using LLM and CNNscited by 0
  22. 2026THEIA: A Multimodal Dataset and Benchmark for Vision-Language Analysis of Layoutcited by 0
  23. 2026cktFormer: Transformer-Based Approach for Automated Analog Circuit Designcited by 0