mlsanityData to 14 Oct 2026

The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation

arXiv 2509.20215 ↗First posted 24 Sep 2025cs.AR cs.AI cs.SEcited by 1

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Abstract (arXiv)

LLMs face significant challenges in Verilog generation due to limited domain-specific knowledge. While sampling techniques improve pass@k metrics, hardware engineers need one trustworthy solution rather than uncertain candidates. To bridge this gap, we formulate it as a semantic alignment problem between requirements and Verilog implementations, and propose VCD-RNK, a discriminator model tailored for efficient Verilog code reranking. Specifically, VCD-RNKincorporates Verilog-specific reasoning by distilling expert knowledge across three dimensions: code semantic analysis, test case generation, and functional correctness assessment. By explicitly simulating the above reasoning processes during inference, VCD-RNK effectively avoids computationally intensive test execution in existing methods.

Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 12 of its 17 references that are in the map. First posted on arXiv 24 Sep 2025.

Builds on

12 of 17 references.

References · 12

  1. 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,380
  2. 2022CodeT: Code Generation with Generated Testscited by 384
  3. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  4. 2024Continual Learning of Large Language Models: A Comprehensive Surveycited by 234
  5. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  6. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  7. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  8. 2025Seed-Coder: Let the Code Model Curate Data for Itselfcited by 49
  9. 2023Chain-of-Thought in Neural Code Generation: From and For Lightweight Language Modelscited by 27
  10. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  11. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 13
  12. 2024Towards Cross-Domain Continual Learningcited by 2

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Cited by year

Citing papers per year: 2025: 1.

1 paper.

  1. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8

Similar, not cited

Close in wording, no citation either way

  1. 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
  2. 2026Execution-Anchored Hallucination Calibration Reranking for Verilog Code Generation ↗
  3. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
  4. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
  5. 2026Semantic Consensus Decoding: Backdoor Defense for Verilog Code Generation
  6. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
  7. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
  8. 2025VFlow: Discovering Optimal Agentic Workflows for Verilog Generation