mlsanityData to 7 Oct 2026

VeriGen: A Large Language Model for Verilog Code Generation

arXiv 2308.00708 ↗First posted 28 Jul 2023cs.PL cs.LG cs.SEcited by 197

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Cited by 37 in LLM agents and tool use, but placed by its own abstract, which didn’t fit.

Abstract (arXiv)

In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and modeling digital systems. We fine-tune pre-existing LLMs on Verilog datasets compiled from GitHub and Verilog textbooks. We evaluate the functional correctness of the generated Verilog code using a specially designed test suite, featuring a custom problem set and testing benches. Here, our fine-tuned open-source CodeGen-16B model outperforms the commercial state-of-the-art GPT-3.5-turbo model with a 1.1% overall increase. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.

Key facts. Cited by 197 papers in the map (data through 7 Oct 2026). Builds on 21 of its 38 references that are in the map. First posted on arXiv 28 Jul 2023.

Builds on

21 of 38 references.

References · 21

  1. 2017Attention Is All You Needcited by 59,932
  2. 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,204
  3. 2020Language Models are Few-Shot Learnerscited by 32,199
  4. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  5. 2022PaLM: Scaling Language Modeling with Pathwayscited by 5,304
  6. 2020The Pile: An 800GB Dataset of Diverse Text for Language Modelingcited by 2,346
  7. 2019Megatron-LM: Training Multi-Billion Parameter Language Models Using Model Parallelismcited by 1,829
  8. 2023StarCoder: may the source be with you!cited by 790
  9. 2019CodeSearchNet Challenge: Evaluating the State of Semantic Code Searchcited by 638
  10. 2021Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributionscited by 417
  11. 2021ZeRO-Offload: Democratizing Billion-Scale Model Trainingcited by 339
  12. 2021ZeRO-Infinity: Breaking the GPU Memory Wall for Extreme Scale Deep Learningcited by 253
9 more
  1. 2023A Comprehensive Capability Analysis of GPT-3 and GPT-3.5 Series Modelscited by 244
  2. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  3. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
  4. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  5. 2022Lost at C: A User Study on the Security Implications of Large Language Model Code Assistantscited by 87
  6. 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
  7. 2023Towards Human-Bot Collaborative Software Architecting with ChatGPTcited by 31
  8. 2023Fixing Hardware Security Bugs with Large Language Modelscited by 24
  9. 2017PrivMin: Differentially Private MinHash for Jaccard Similarity Computationcited by 5

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2023: 7; 2024: 43; 2025: 87; 2026: 60.

197 papers.

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  1. 2023Large Language Models for Software Engineering: A Systematic Literature Reviewcited by 389
  2. 2024Improved Techniques for Optimization-Based Jailbreaking on Large Language Modelscited by 98
  3. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  4. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  5. 2023Unifying the Perspectives of NLP and Software Engineering: A Survey on Language Models for Codecited by 62
  6. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
  7. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  8. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  9. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  10. 2024Large Language Model Inference Acceleration: A Comprehensive Hardware Perspectivecited by 36
  11. 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 35
  12. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
38 more
  1. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
  2. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  3. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 25
  4. 2023TypeFly: Flying Drones with Large Language Modelcited by 23
  5. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  6. 2023LLM for SoC Security: A Paradigm Shiftcited by 22
  7. 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
  8. 2024LLM4PLC: Harnessing Large Language Models for Verifiable Programming of PLCs in Industrial Control Systemscited by 20
  9. 2024CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generationcited by 19
  10. 2025VFlow: Discovering Optimal Agentic Workflows for Verilog Generationcited by 19
  11. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
  12. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  13. 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 16
  14. 2024AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAGcited by 16
  15. 2025SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoningcited by 16
  16. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  17. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 16
  18. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  19. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
  20. 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
  21. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 14
  22. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  23. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
  24. 2024The Impact of Prompt Programming on Function-Level Code Generationcited by 13
  25. 2025From Code Foundation Models to Agents and Applications: A Comprehensive Survey and Practical Guide to Code Intelligencecited by 13
  26. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  27. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  28. 2024LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generationcited by 11
  29. 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
  30. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
  31. 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
  32. 2024Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledgecited by 10
  33. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  34. 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Datasetcited by 10
  35. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 10
  36. 2025HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Taskscited by 10
  37. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
  38. 2025DeepRTL2: A Versatile Model for RTL-Related Taskscited by 10

50 most cited of 197 All 197 (JSON)