mlsanityData to 7 Oct 2026

Report for NSF Workshop on AI for Electronic Design Automation

arXiv 2601.14541 ↗First posted 20 Jan 2026cs.LG cs.AI cs.ARcited by 1

Not on the map. Why?

Abstract (arXiv)

This report distills the discussions and recommendations from the NSF Workshop on AI for Electronic Design Automation (EDA), held on December 10, 2024 in Vancouver alongside NeurIPS 2024. Bringing together experts across machine learning and EDA, the workshop examined how AI-spanning large language models (LLMs), graph neural networks (GNNs), reinforcement learning (RL), neurosymbolic methods, etc.-can facilitate EDA and shorten design turnaround. The workshop includes four themes: (1) AI for physical synthesis and design for manufacturing (DFM), discussing challenges in physical manufacturing process and potential AI applications; (2) AI for high-level and logic-level synthesis (HLS/LLS), covering pragma insertion, program transformation, RTL code generation, etc.; (3) AI toolbox for optimization and design, discussing frontier AI developments that could potentially be applied to EDA tasks; and (4) AI for test and verification, including LLM-assisted verification tools, ML-augmented SAT solving, security/reliability challenges, etc. The report recommends NSF to foster AI/EDA collaboration, invest in foundational AI for EDA, develop robust data infrastructures, promote scalable compute infrastructure, and invest in workforce development to democratize hardware design and enable next-generation hardware systems. The workshop information can be found on the website https://ai4eda-workshop.github.io/.

Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 30 of its 130 references that are in the map. First posted on arXiv 20 Jan 2026.

Builds on

30 of 130 references.

References · 30

  1. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  2. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  3. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  4. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  5. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  6. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  7. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
  8. 2019DRiLLS: Deep Reinforcement Learning for Logic Synthesiscited by 47
  9. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
  10. 2023Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networkscited by 27
  11. 2020AutoDSE: Enabling Software Programmers to Design Efficient FPGA Acceleratorscited by 25
  12. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
18 more
  1. 2021ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representationcited by 21
  2. 2021DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networkscited by 18
  3. 2019Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Designcited by 17
  4. 2022NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulationcited by 17
  5. 2024Allo: A Programming Model for Composable Accelerator Designcited by 16
  6. 2024DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agentcited by 15
  7. 2024RLSF: Fine-tuning LLMs via Symbolic Feedbackcited by 13
  8. 2024Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesiscited by 10
  9. 2023HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesiscited by 9
  10. 2024Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesiscited by 9
  11. 2024A Unified Framework for Automated Code Transformation and Pragma Insertioncited by 5
  12. 2025Stream-HLS: Towards Automatic Dataflow Accelerationcited by 5
  13. 2023AISYN: AI-driven Reinforcement Learning-Based Logic Synthesis Frameworkcited by 4
  14. 2024Efficient Task Transfer for HLS DSEcited by 4
  15. 2020Design Rule Checking with a CNN Based Feature Extractorcited by 3
  16. 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Searchcited by 3
  17. 2024OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesiscited by 3
  18. 2025Silent Data Corruption by 10x Test Escapes Threatens Reliable Computingcited by 3

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2026: 1.

1 paper.

  1. 2026SwiftCTS: Fast Cross-Design Prediction and Pareto Optimization of Clock Tree Metrics via Few-Shot Calibrationcited by 0