mlsanityData to 7 Oct 2026

OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

arXiv 2407.16237 ↗First posted 23 Jul 2024cs.AR cs.AI cs.LGcited by 56

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Abstract (arXiv)

Recent studies have demonstrated the significant potential of Large Language Models (LLMs) in generating Register Transfer Level (RTL) code, with notable advancements showcased by commercial models such as GPT-4 and Claude3-Opus. However, these proprietary LLMs often raise concerns regarding privacy and security. While open-source LLMs offer solutions to these concerns, they typically underperform commercial models in RTL code generation tasks, primarily due to the scarcity of high-quality open-source RTL datasets. To address this challenge, we introduce OriGen , a fully open-source framework that incorporates self-reflection capabilities and a novel dataset augmentation methodology for generating high-quality, large-scale RTL code. Our approach employs a code-tocode augmentation technique to enhance the quality of open-source RTL code datasets. Furthermore, OriGen can rectify syntactic errors through a self-reflection process that leverages compiler feedback. Experimental results demonstrate that OriGen significantly outperforms other open-source alternatives in RTL code generation. It surpasses the previous best-performing open-source LLM by 12.8% and even exceeds GPT-4 Turbo in the pass@1 metric on the VerilogEval-Human benchmark. Moreover, OriGen exhibits superior capabilities in self-reflection and error correction, outperforming GPT-4 by 19.9% on a benchmark designed to evaluate self-reflection capabilities.

Key facts. Cited by 56 papers in the map (data through 7 Oct 2026). Builds on 17 of its 34 references that are in the map. First posted on arXiv 23 Jul 2024.

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17 of 34 references.

References · 17

  1. 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,084
  2. 2023Code Llama: Open Foundation Models for Codecited by 2,105
  3. 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,154
  4. 2024StarCoder 2 and The Stack v2: The Next Generationcited by 484
  5. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  6. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  7. 2021AMMUS : A Survey of Transformer-based Pretrained Models in Natural Language Processingcited by 131
  8. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
  9. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
  10. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  11. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  12. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
5 more
  1. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 69
  2. 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
  3. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  4. 2023A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automationcited by 10
  5. 2021TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebracited by 5

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2024: 4; 2025: 30; 2026: 22.

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  1. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 41
  2. 2024Low-Rank Adaptation for Foundation Models: A Comprehensive Reviewcited by 35
  3. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
  4. 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
  5. 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
  6. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  7. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  8. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 16
  9. 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
  10. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  11. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  12. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
38 more
  1. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
  2. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 10
  3. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
  4. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 8
  5. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  6. 2025LLM-DSE: Searching Accelerator Parameters with LLM Agentscited by 7
  7. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  8. 2026Agentic Hardware Design as Repository-Level Code Evolutioncited by 6
  9. 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMscited by 4
  10. 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
  11. 2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Modelscited by 4
  12. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
  13. 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generationcited by 4
  14. 2026CktEvo: Repository-Level RTL Code Benchmark for Design Evolutioncited by 3
  15. 2025Speculative Decoding for Verilog: Speed and Quality, All in Onecited by 2
  16. 2025Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMscited by 2
  17. 2025hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generationcited by 2
  18. 2025EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generationcited by 2
  19. 2025AgenticTCAD: A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimizationcited by 2
  20. 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generationcited by 2
  21. 2025Iceberg: Enhancing HLS Modeling with Synthetic Datacited by 1
  22. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
  23. 2025Breaking Memorization Barriers in LLM Code Fine-Tuning via Information Bottleneck for Improved Generalizationcited by 1
  24. 2026QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generationcited by 1
  25. 2026UCAgent: An End-to-End Agent for Block-Level Functional Verificationcited by 1
  26. 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generationcited by 1
  27. 2026TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilogcited by 1
  28. 2026ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generationcited by 1
  29. 2025Lorecast: Layout-Aware Performance and Power Forecasting from Natural Languagecited by 0
  30. 2025RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Expertscited by 0
  31. 2025VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learningcited by 0
  32. 2025PEFA-AI: Advancing Open-source LLMs for RTL generation using Progressive Error Feedback Agentic-AIcited by 0
  33. 2026The New Compiler Stack: A Survey on the Synergy of LLMs and Compilerscited by 0
  34. 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learningcited by 0
  35. 2026ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestrationcited by 0
  36. 2026LEGO: An LLM Skill-Based Front-End Design Generation Platformcited by 0
  37. 2026Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generationcited by 0
  38. 2026UniRTL: Unifying Code and Graph for Robust RTL Representation Learningcited by 0

50 most cited of 56 All 56 (JSON)