mlsanityData to 14 Oct 2026

CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference

arXiv 2511.16395 ↗First posted 20 Nov 2025cs.AI cs.PL cs.SEcited by 3

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Abstract (arXiv)

Large Language Models (LLMs) have demonstrated remarkable potential in hardware front-end design using hardware description languages (HDLs). However, their inherent tendency toward hallucination often introduces functional errors into the generated HDL designs. To address this issue, we propose the framework CorrectHDL that leverages high-level synthesis (HLS) results as functional references to correct potential errors in LLM-generated HDL designs.The input to the proposed framework is a C/C++ program that specifies the target circuit's functionality. The program is provided to an LLM to directly generate an HDL design, whose syntax errors are repaired using a Retrieval-Augmented Generation (RAG) mechanism. The functional correctness of the LLM-generated circuit is iteratively improved by comparing its simulated behavior with an HLS reference design produced by conventional HLS tools, which ensures the functional correctness of the result but can lead to suboptimal area and power efficiency. Experimental results demonstrate that circuits generated by the proposed framework achieve significantly better area and power efficiency than conventional HLS designs and approach the quality of human-engineered circuits. Meanwhile, the correctness of the resulting HDL implementation is maintained, highlighting the effectiveness and potential of agentic HDL design leveraging the generative capabilities of LLMs and the rigor of traditional correctness-driven IC design flows.

Key facts. Cited by 3 papers in the map (data through 14 Oct 2026). Builds on 26 of its 52 references that are in the map. First posted on arXiv 20 Nov 2025.

Builds on

26 of 52 references.

References · 26

  1. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  3. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  4. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  5. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  6. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  7. 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 43
  8. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 41
  9. 2024AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
  10. 2020AutoDSE: Enabling Software Programmers to Design Efficient FPGA Acceleratorscited by 25
  11. 2024HLSPilot: LLM-based High-Level Synthesiscited by 25
  12. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
14 more
  1. 2024CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Designcited by 24
  2. 2024C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gapcited by 16
  3. 2024C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?cited by 12
  4. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
  5. 2024LLM-Aided Efficient Hardware Design Automationcited by 11
  6. 2025VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistencycited by 11
  7. 2025HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Taskscited by 10
  8. 2024Comparing large language models and human programmers for generating programming codecited by 9
  9. 2025Can Reasoning Models Reason about Hardware? An Agentic HLS Perspectivecited by 9
  10. 2025Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Formcited by 7
  11. 2025Paradigm-Based Automatic HDL Code Generation Using LLMscited by 6
  12. 2023Logic Design of Neural Networks for High-Throughput and Low-Power Applicationscited by 4
  13. 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoningcited by 4
  14. 2025MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Designcited by 1

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 3.

3 papers.

  1. 2026Evidence-Driven LLM Agent for C-to-Synthesizable-C Conversion and Verificationcited by 1
  2. 2026LLM for EDA in Front-End Design: Challenges and Opportunitiescited by 0
  3. 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL
  2. 2025Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
  3. 2025SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
  4. 2024New Solutions on LLM Acceleration, Optimization, and Application
  5. 2026Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
  6. 2026Can Agents Design Better Chips with a Higher Level Abstraction?
  7. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
  8. 2025TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization