mlsanityData to 7 Oct 2026

DAVE: Deriving Automatically Verilog from English

arXiv 2009.01026 ↗First posted 27 Aug 2020cs.SE cs.CL cs.LGcited by 46

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Abstract (arXiv)

While specifications for digital systems are provided in natural language, engineers undertake significant efforts to translate them into the programming languages understood by compilers for digital systems. Automating this process allows designers to work with the language in which they are most comfortable --the original natural language -- and focus instead on other downstream design challenges. We explore the use of state-of-the-art machine learning (ML) to automatically derive Verilog snippets from English via fine-tuning GPT-2, a natural language ML system. We describe our approach for producing a suitable dataset of novice-level digital design tasks and provide a detailed exploration of GPT-2, finding encouraging translation performance across our task sets (94.8% correct), with the ability to handle both simple and abstract design tasks.

Key facts. Cited by 46 papers in the map (data through 7 Oct 2026). First posted on arXiv 27 Aug 2020.

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Citing papers per year: 2021: 1; 2022: 1; 2023: 8; 2024: 17; 2025: 14; 2026: 5.

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  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  3. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  4. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
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  6. 2024A Survey on LLM-based Code Generation for Low-Resource and Domain-Specific Programming Languagescited by 65
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  9. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  10. 2023(Security) Assertions by Large Language Modelscited by 31
  11. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  12. 2024CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generationcited by 19
34 more
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  2. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  3. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  4. 2023A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automationcited by 10
  5. 2024FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardwarecited by 9
  6. 2024CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generationcited by 9
  7. 2024Evaluating LLMs for Hardware Design and Testcited by 8
  8. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  9. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMscited by 7
  10. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  11. 2024SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generationcited by 5
  12. 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflectioncited by 5
  13. 2025Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarizationcited by 5
  14. 2024Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Modelscited by 4
  15. 2024Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024)cited by 4
  16. 2025Towards LLM-based Root Cause Analysis of Hardware Design Failurescited by 4
  17. 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
  18. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
  19. 2024LLM-aided explanations of EDA synthesis errorscited by 3
  20. 2024Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Promptingcited by 3
  21. 2025Large Language Models (LLMs) for Electronic Design Automation (EDA)cited by 3
  22. 2023Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Designcited by 2
  23. 2025TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generatorcited by 2
  24. 2025Speculative Decoding for Verilog: Speed and Quality, All in Onecited by 2
  25. 2023Towards the Imagenets of ML4EDAcited by 1
  26. 2024ChipXplore: Natural Language Exploration of Hardware Designs and Librariescited by 1
  27. 2025Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniquescited by 1
  28. 2025QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Designcited by 1
  29. 2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Modelscited by 1
  30. 2023A Machine Learning Approach Towards SKILL Code Autocompletioncited by 0
  31. 2025QiMeng: Fully Automated Hardware and Software Design for Processor Chipcited by 0
  32. 2026Automated Generation of Microfluidic Netlists using Large Language Modelscited by 0
  33. 2026CktFormalizer: Autoformalization of Natural Language into Circuit Representationscited by 0
  34. 2026OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Designcited by 0