mlsanityData to 7 Oct 2026

Towards LLM-based Root Cause Analysis of Hardware Design Failures

arXiv 2507.06512 ↗First posted 9 Jul 2025cs.AR cs.AIcited by 4

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Abstract (arXiv)

With advances in large language models (LLMs), new opportunities have emerged to develop tools that support the digital hardware design process. In this work, we explore how LLMs can assist with explaining the root cause of design issues and bugs that are revealed during synthesis and simulation, a necessary milestone on the pathway towards widespread use of LLMs in the hardware design process and for hardware security analysis. We find promising results: for our corpus of 34 different buggy scenarios, OpenAI's o3-mini reasoning model reached a correct determination 100% of the time under pass@5 scoring, with other state of the art models and configurations usually achieving more than 80% performance and more than 90% when assisted with retrieval-augmented generation.

Key facts. Cited by 4 papers in the map (data through 7 Oct 2026). Builds on 14 of its 23 references that are in the map. First posted on arXiv 9 Jul 2025.

Builds on

14 of 23 references.

References · 14

  1. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  2. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  3. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  4. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  5. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
  6. 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
  7. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  8. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 38
  9. 2023(Security) Assertions by Large Language Modelscited by 31
  10. 2023Fixing Hardware Security Bugs with Large Language Modelscited by 24
  11. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  12. 2023Dcc --help: Generating Context-Aware Compiler Error Explanations with Large Language Modelscited by 11
2 more
  1. 2024LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verificationcited by 6
  2. 2024LLM-aided explanations of EDA synthesis errorscited by 3

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2026: 4.

4 papers.

  1. 2026QiMeng-PRepair: Precise Code Repair via Edit-Aware Reward Optimizationcited by 1
  2. 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detectioncited by 0
  3. 2026EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysiscited by 0
  4. 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestrationcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026A Survey on LLM-Integrated Hardware Design Verification
  2. 2026LAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns
  3. 2026How LLMs Fail and Generalize in RTL Coding for Hardware Design?
  4. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
  5. 2026LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflow
  6. 2026HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking
  7. 2026Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
  8. 2025Evaluating LLMs and Prompting Strategies for Automated Hardware Diagnosis from Textual User-Reports