mlsanityData to 14 Oct 2026

LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration

arXiv 2608.27184 ↗First posted 27 Aug 2026cs.AR cs.AI cs.SEcited by 1

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Abstract (arXiv)

Electronic design automation (EDA) has advanced engineering productivity through successive generations of tooling that progressively automate synthesis, optimisation, and verification. Large language models (LLMs) extend this trajectory by enabling direct translation from design intent to hardware implementations. In most of the EDA literature, LLM-based solutions are typically assisting siloed design stages or tasks, however this obscured the drivers by which capability emerges and systems scale. In this Perspective, we instead define three hierarchical roles that reveal how capability accumulates: a Generator that produces design artifacts in a single pass, an Agent that refines outputs through iterative tool feedback, and an Orchestrator that coordinates decisions across EDA-stages. Across published systems, this reveals a syntax trap in which models are trained to produce plausible code rather than physically correct hardware, compounded by fragmented tools and loss of design context that obscure how decisions affect later stages. Comparisons across the three roles show that current approaches struggle to scale to industrial designs, motivating a shift towards a standardised, physics-aware orchestrator that connects tools and agents across the EDA flow for more reliable and accessible hardware design.

Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 52 of its 69 references that are in the map. First posted on arXiv 27 Aug 2026.

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52 of 69 references.

References · 52

  1. 2023The Impact of AI on Developer Productivity: Evidence from GitHub Copilotcited by 274
  2. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  3. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  4. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  5. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  6. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  7. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 122
  8. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  9. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  10. 2025A survey of agent interoperability protocols: Model Context Protocol (MCP), Agent Communication Protocol (ACP), Agent-to-Agent Protocol (A2A), and Agent Network Protocol (ANP)cited by 101
  11. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  12. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
38 more
  1. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  2. 2021Machine Learning for Electronic Design Automation: A Surveycited by 72
  3. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  4. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 44
  5. 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 43
  6. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  7. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
  8. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  9. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  10. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 31
  11. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  12. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 19
  13. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  14. 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
  15. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  16. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  17. 2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
  18. 2024The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Modelscited by 12
  19. 2025Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automationcited by 12
  20. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metriccited by 12
  21. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMscited by 12
  22. 2025RTLSquad: Multi-Agent Based Interpretable RTL Designcited by 9
  23. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 9
  24. 2025From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verificationcited by 9
  25. 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
  26. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  27. 2025The Dawn of Agentic EDA: A Survey of Autonomous Digital Chip Designcited by 7
  28. 2020Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standardscited by 6
  29. 2025AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agentscited by 6
  30. 2024DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representationscited by 5
  31. 2025ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awarenesscited by 5
  32. 2025LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Modelscited by 5
  33. 2025Towards LLM-based Root Cause Analysis of Hardware Design Failurescited by 4
  34. 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoningcited by 4
  35. 2025CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMscited by 3
  36. 2025Large Language Models (LLMs) for Electronic Design Automation (EDA)cited by 3
  37. 2025VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Promptscited by 2
  38. 2026A flexible language model-assisted electronic design automation frameworkcited by 2

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