mlsanityData to 14 Oct 2026

SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design

arXiv 2506.02089 ↗First posted 2 Jun 2025cs.LG cs.AI cs.CRcited by 12

On the map: LLM safety and security → Backdoor and data poisoning attacks

Abstract (arXiv)

Large Language Models (LLMs) offer transformative capabilities for hardware design automation, particularly in Verilog code generation. However, they also pose significant data security challenges, including Verilog evaluation data contamination, intellectual property (IP) design leakage, and the risk of malicious Verilog generation. We introduce SALAD, a comprehensive assessment that leverages machine unlearning to mitigate these threats. Our approach enables the selective removal of contaminated benchmarks, sensitive IP and design artifacts, or malicious code patterns from pre-trained LLMs, all without requiring full retraining. Through detailed case studies, we demonstrate how machine unlearning techniques effectively reduce data security risks in LLM-aided hardware design.

Key facts. Cited by 12 papers in the map (data through 14 Oct 2026). Placed in Backdoor and data poisoning attacks, one of 12 directions in LLM safety and security. Builds on 46 of its 67 references that are in the map. First posted on arXiv 2 Jun 2025.

Builds on

46 of 67 references.

Closest ancestors · 3

Same direction, newest first

  1. 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation26 Nov
  2. 2023A Comprehensive Overview of Backdoor Attacks in Large Language Models within Communication Networks28 Aug
  3. 2021CoProtector: Protect Open-Source Code against Unauthorized Training Usage with Data Poisoning25 Oct

Other references · 43

  1. 2023Llama 2: Open Foundation and Fine-Tuned Chat Modelscited by 13,028
  2. 2020Extracting Training Data from Large Language Modelscited by 2,189
  3. 2024TOFU: A Task of Fictitious Unlearning for LLMscited by 533
  4. 2024The WMDP Benchmark: Measuring and Reducing Malicious Use With Unlearningcited by 509
  5. 2024Negative Preference Optimization: From Catastrophic Collapse to Effective Unlearningcited by 504
  6. 2021Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributionscited by 431
  7. 2023Detecting Pretraining Data from Large Language Modelscited by 387
  8. 2024Rethinking Machine Unlearning for Large Language Modelscited by 257
  9. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  10. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  11. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  12. 2024Simplicity Prevails: Rethinking Negative Preference Optimization for LLM Unlearningcited by 172
31 more
  1. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  2. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  3. 2020You Autocomplete Me: Poisoning Vulnerabilities in Neural Code Completioncited by 131
  4. 2024The Emerged Security and Privacy of LLM Agent: A Survey with Case Studiescited by 131
  5. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 122
  6. 2024Large Language Model Unlearning via Embedding-Corrupted Promptscited by 116
  7. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  8. 2024Min-K%++: Improved Baseline for Detecting Pre-Training Data from Large Language Modelscited by 103
  9. 2024Reversing the Forget-Retain Objectives: An Efficient LLM Unlearning Framework from Logit Differencecited by 88
  10. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  11. 2024LLM Unlearning via Loss Adjustment with Only Forget Datacited by 75
  12. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
  13. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  14. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  15. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  16. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 41
  17. 2023Controlling the Extraction of Memorized Data from Large Language Models via Prompt-Tuningcited by 40
  18. 2022Privacy Adhering Machine Un-learning in NLPcited by 36
  19. 2024Survey of different Large Language Model Architectures: Trends, Benchmarks, and Challengescited by 32
  20. 2024AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
  21. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 26
  22. 2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineerscited by 25
  23. 2024PreCurious: How Innocent Pre-Trained Language Models Turn into Privacy Trapscited by 23
  24. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  25. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 20
  26. 2024Cross-Lingual Unlearning of Selective Knowledge in Multilingual Language Modelscited by 20
  27. 2024LLM-Aided Testbench Generation and Bug Detection for Finite-State Machinescited by 17
  28. 2024Privacy in Fine-tuning Large Language Models: Attacks, Defenses, and Future Directionscited by 14
  29. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  30. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
  31. 2022CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution (Extended Version)cited by 2

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 5; 2026: 7.

12 papers.

  1. 2025NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestrationcited by 9
  2. 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimizationcited by 5
  3. 2025Large Language Models (LLMs) for Electronic Design Automation (EDA)cited by 3
  4. 2025CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Referencecited by 3
  5. 2026HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarkingcited by 3
  6. 2026TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertioncited by 2
  7. 2026SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generationcited by 2
  8. 2025When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generationcited by 1
  9. 2026GUIDE: GenAI Units In Digital Design Educationcited by 1
  10. 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
  11. 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Modelscited by 0
  12. 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2025Towards LLM-based Root Cause Analysis of Hardware Design Failures
  2. 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection
  3. 2026Semantic Consensus Decoding: Backdoor Defense for Verilog Code Generation
  4. 2026Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
  5. 2025SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip
  6. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
  7. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
  8. 2026LAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns