mlsanityData to 14 Oct 2026

Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection

arXiv 2604.13298 ↗First posted 14 Apr 2026cs.CRcited by 3

On the map: LLM agents and tool use → Agent threats, guardrails and governance

Abstract (arXiv)

The globalization of integrated circuit (IC) design and manufacturing has increased the exposure of hardware intellectual property (IP) to untrusted stages of the supply chain, raising concerns about reverse engineering, piracy, tampering, and overbuilding. Hardware netlist obfuscation is a promising countermeasure, but automating the generation of functionally correct and security-relevant obfuscated circuits remains challenging, particularly for benchmark-scale designs. This paper presents an agentic, large language model (LLM)-driven framework for automated hardware netlist obfuscation. The proposed framework combines retrieval-grounded planning, structured lock-plan generation, deterministic netlist compilation, functional verification, and SAT-based security evaluation. Rather than a single prompt-to-output generation step, the framework decomposes the task into specialized stages for circuit analysis, synthesis, verification, and attack evaluation. We evaluate the framework on ISCAS-85 benchmarks using functional equivalence checking and SAT-based attacks. Results show that the framework generates correct locked netlists while introducing measurable output corruption under incorrect keys, while SAT attacks remain effective. These findings highlight both the potential and current limitations of agentic LLM-driven obfuscation.

Key facts. Cited by 3 papers in the map (data through 14 Oct 2026). Placed in Agent threats, guardrails and governance, one of 16 directions in LLM agents and tool use. Builds on 20 of its 40 references that are in the map. First posted on arXiv 14 Apr 2026.

Builds on

20 of 40 references.

References · 20

  1. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  2. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  3. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  4. 2025SagaLLM: Context Management, Validation, and Transaction Guarantees for Multi-Agent LLM Planningcited by 60
  5. 2024Formal-LLM: Integrating Formal Language and Natural Language for Controllable LLM-based Agentscited by 40
  6. 2025Flow: Modularized Agentic Workflow Automationcited by 34
  7. 2024AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
  8. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 26
  9. 2024ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generationcited by 16
  10. 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
  11. 2025Self-Organizing Agent Network for LLM-based Workflow Automationcited by 12
  12. 2024Robust Planning with Compound LLM Architectures: An LLM-Modulo Approachcited by 9
8 more
  1. 2023HW-V2W-Map: Hardware Vulnerability to Weakness Mapping Framework for Root Cause Analysis with GPT-assisted Mitigation Suggestioncited by 8
  2. 2024SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisionscited by 4
  3. 2025Large Language Models and Attention-Based AI for Hardware Design and Security: Progress, Challenges, and Opportunitiescited by 4
  4. 2024Automated Hardware Logic Obfuscation Framework Using GPTcited by 3
  5. 2025Transformers for Secure Hardware Systems: Applications, Challenges, and Outlookcited by 2
  6. 2025LLM-HyPZ: Hardware Vulnerability Discovery using an LLM-Assisted Hybrid Platform for Zero-Shot Knowledge Extraction and Refinementcited by 2
  7. 2024CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attackscited by 1
  8. 2024SubLock: Sub-Circuit Replacement based Input Dependent Key-based Logic Locking for Robust IP Protectioncited by 1

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 3.

3 papers.

  1. 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
  2. 2026VeriChat: An Agentic Conversational AI Assistant for Hardware Security Verificationcited by 0
  3. 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking
  2. 2025MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models
  3. 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection
  4. 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
  5. 2026AgentDV: Closed-Loop Agentic AI for Hardware Design Verification
  6. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design
  7. 2025Red Teaming Methodology for Design Obfuscation ↗
  8. 2025ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification