mlsanityData to 7 Oct 2026

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust

arXiv 2405.07061 ↗First posted 11 May 2024cs.LG cs.AR cs.CRcited by 18

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Abstract (arXiv)

Chip design is about to be revolutionized by the integration of large language, multimodal, and circuit models (collectively LxMs). While exploring this exciting frontier with tremendous potential, the community must also carefully consider the related security risks and the need for building trust into using LxMs for chip design. First, we review the recent surge of using LxMs for chip design in general. We cover state-of-the-art works for the automation of hardware description language code generation and for scripting and guidance of essential but cumbersome tasks for electronic design automation tools, e.g., design-space exploration, tuning, or designer training. Second, we raise and provide initial answers to novel research questions on critical issues for security and trustworthiness of LxM-powered chip design from both the attack and defense perspectives.

Key facts. Cited by 18 papers in the map (data through 7 Oct 2026). Builds on 38 of its 58 references that are in the map. First posted on arXiv 11 May 2024.

Builds on

38 of 58 references.

References · 38

  1. 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,204
  2. 2023Llama 2: Open Foundation and Fine-Tuned Chat Modelscited by 12,865
  3. 2020Retrieval-Augmented Generation for Knowledge-Intensive NLP Taskscited by 9,160
  4. 2022ReAct: Synergizing Reasoning and Acting in Language Modelscited by 8,355
  5. 2021Finetuned Language Models Are Zero-Shot Learnerscited by 3,747
  6. 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 876
  7. 2023Instruction Tuning for Large Language Models: A Surveycited by 617
  8. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  9. 2023GraphGPT: Graph Instruction Tuning for Large Language Modelscited by 223
  10. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  11. 2023Multimodal Large Language Models: A Surveycited by 193
  12. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
26 more
  1. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  2. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  3. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
  4. 2021Examining Zero-Shot Vulnerability Repair with Large Language Modelscited by 105
  5. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  6. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  7. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  8. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  9. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
  10. 2018Spectre Attacks: Exploiting Speculative Executioncited by 47
  11. 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
  12. 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 42
  13. 2023(Security) Assertions by Large Language Modelscited by 31
  14. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  15. 2023Fixing Hardware Security Bugs with Large Language Modelscited by 24
  16. 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
  17. 2024ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generationcited by 15
  18. 2023DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protectioncited by 12
  19. 2014Managing your Private and Public Data: Bringing down Inference Attacks against your Privacycited by 10
  20. 2021Fuzzing Hardware Like Softwarecited by 9
  21. 2023Unlocking Hardware Security Assurance: The Potential of LLMscited by 9
  22. 2024SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Modelcited by 9
  23. 2020Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDAcited by 4
  24. 2023New Interaction Paradigm for Complex EDA Software Leveraging GPTcited by 4
  25. 2020Hardware Security for and beyond CMOS Technologycited by 3
  26. 2023SCAR: Power Side-Channel Analysis at RTL-Levelcited by 3

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 10; 2026: 8.

18 papers.

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  1. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  2. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 10
  3. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
  4. 2025NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestrationcited by 8
  5. 2025LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMscited by 5
  6. 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimizationcited by 5
  7. 2025From Trace to Line: LLM Agent for Real-World OSS Vulnerability Localizationcited by 4
  8. 2025Large Language Models (LLMs) for Electronic Design Automation (EDA)cited by 3
  9. 2026TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertioncited by 2
  10. 2026VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilogcited by 2
  11. 2025A Survey: Towards Privacy and Security in Mobile Large Language Modelscited by 1
  12. 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generationcited by 1
6 more
  1. 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
  2. 2025RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Expertscited by 0
  3. 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Modelscited by 0
  4. 2026VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluationcited by 0
  5. 2026Surveying GenAI-based Automation in Printed Circuit Board Design and Testcited by 0
  6. 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0