mlsanityData to 7 Oct 2026

Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS

arXiv 2402.03289 ↗First posted 5 Feb 2024cs.LG cs.AI cs.ARcited by 42

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Abstract (arXiv)

Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency. This is due to the lack of PPA awareness in conventional transformer decoding algorithms. In response, we present an automated transformer decoding algorithm that integrates Monte Carlo tree-search for lookahead, guiding the transformer to produce compilable, functionally correct, and PPA-optimized code. Empirical evaluation with a fine-tuned language model on RTL codesets shows that our proposed technique consistently generates functionally correct code compared to prompting-only methods and effectively addresses the PPA-unawareness drawback of naive large language models. For the largest design generated by the state-of-the-art LLM (16-bit adder), our technique can achieve a 31.8% improvement in the area-delay product.

Key facts. Cited by 42 papers in the map (data through 7 Oct 2026). Builds on 12 of its 20 references that are in the map. First posted on arXiv 5 Feb 2024.

Builds on

12 of 20 references.

References · 12

  1. 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,204
  2. 2019Exploring the Limits of Transfer Learning with a Unified Text-to-Text Transformercited by 14,491
  3. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  4. 2020CodeBERT: A Pre-Trained Model for Programming and Natural Languagescited by 1,286
  5. 2021CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for Code Understanding and Generationcited by 890
  6. 2020GraphCodeBERT: Pre-training Code Representations with Data Flowcited by 600
  7. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  8. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  9. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  10. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  11. 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
  12. 2023(Security) Assertions by Large Language Modelscited by 31

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2024: 13; 2025: 20; 2026: 9.

42 papers.

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  1. 2025Can We Generate Images with CoT? Let's Verify and Reinforce Image Generation Step by Stepcited by 130
  2. 2025LLM Post-Training: A Deep Dive into Reasoning Large Language Modelscited by 129
  3. 2025Monte Carlo Tree Search for Comprehensive Exploration in LLM-Based Automatic Heuristic Designcited by 100
  4. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  5. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 41
  6. 2025Reasoning Language Models: A Blueprintcited by 41
  7. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  8. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 30
  9. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  10. 2024RethinkMCTS: Refining Erroneous Thoughts in Monte Carlo Tree Search for Code Generationcited by 25
  11. 2025From Passive to Active Reasoning: Can Large Language Models Ask the Right Questions under Incomplete Information?cited by 21
  12. 2024CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generationcited by 19
30 more
  1. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
  2. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  3. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 14
  4. 2025Navigating the Alpha Jungle: An LLM-Powered MCTS Framework for Formulaic Factor Miningcited by 13
  5. 2024LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generationcited by 11
  6. 2025From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verificationcited by 8
  7. 2024LLMPirate: LLMs for Black-box Hardware IP Piracycited by 7
  8. 2025Can Test-Time Scaling Improve World Foundation Model?cited by 7
  9. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  10. 2026Faithful GRPO: Improving Visual Spatial Reasoning in Multimodal Language Models via Constrained Policy Optimizationcited by 6
  11. 2025ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learningcited by 5
  12. 2024Uncertainty-Guided Likelihood Tree Searchcited by 4
  13. 2025From Token to Line: Enhancing Code Generation with a Long-Term Perspectivecited by 4
  14. 2026Deliberate Evolution: Agentic Reasoning for Sample-Efficient Symbolic Regression with LLMscited by 4
  15. 2025QuArch: A Benchmark for Evaluating LLM Reasoning in Computer Architecturecited by 3
  16. 2025CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Referencecited by 3
  17. 2025Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMscited by 2
  18. 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimizationcited by 2
  19. 2025Customizing a Large Language Model for VHDL Design of High-Performance Microprocessorscited by 1
  20. 2026ARIADNE: Agentic Reward-Informed Adaptive Decision Exploration via Blackboard-Driven MCTS for Competitive Program Generationcited by 1
  21. 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
  22. 2024ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Searchcited by 0
  23. 2025RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Expertscited by 0
  24. 2025ML For Hardware Design Interpretability: Challenges and Opportunitiescited by 0
  25. 2025Towards Stepwise Domain Knowledge-Driven Reasoning Optimization and Reflection Improvementcited by 0
  26. 2025PEFA-AI: Advancing Open-source LLMs for RTL generation using Progressive Error Feedback Agentic-AIcited by 0
  27. 2026The New Compiler Stack: A Survey on the Synergy of LLMs and Compilerscited by 0
  28. 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
  29. 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0
  30. 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestrationcited by 0