mlsanityData to 14 Oct 2026

Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists

arXiv 2508.13157 ↗First posted 27 Jun 2025cs.AR cs.AI cs.CVcited by 7

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Abstract (arXiv)

Large Language Model (LLM) exhibits great potential in designing of analog integrated circuits (IC) because of its excellence in abstraction and generalization for knowledge. However, further development of LLM-based analog ICs heavily relies on textual description of analog ICs, while existing analog ICs are mostly illustrated in image-based circuit diagrams rather than text-based netlists. Converting circuit diagrams to netlists help LLMs to enrich the knowledge of analog IC. Nevertheless, previously proposed conversion frameworks face challenges in further application because of limited support of image styles and circuit elements. Up to now, it still remains a challenging task to effectively convert complex circuit diagrams into netlists. To this end, this paper constructs and opensources a new dataset with rich styles of circuit diagrams as well as balanced distribution of simple and complex analog ICs. And a hybrid framework, named Image2Net, is proposed for practical conversion from circuit diagrams to netlists. The netlist edit distance (NED) is also introduced to precisely assess the difference between the converted netlists and ground truth. Based on our benchmark, Image2Net achieves 80.77% successful rate, which is 34.62%-45.19% higher than previous works. Specifically, the proposed work shows 0.116 averaged NED, which is 62.1%-69.6% lower than state-of-the-arts. Our datasets and benchmark are available at https://github.com/LAD021/ci2n_datasets.

Key facts. Cited by 7 papers in the map (data through 14 Oct 2026). Builds on 10 of its 21 references that are in the map. First posted on arXiv 27 Jun 2025.

Builds on

10 of 21 references.

References · 10

  1. 2018MobileNetV2: Inverted Residuals and Linear Bottleneckscited by 4,795
  2. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  3. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  4. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  5. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  6. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  7. 2024AmpAgent: An LLM-based Multi-Agent System for Multi-stage Amplifier Schematic Design from Literature for Process and Performance Portingcited by 29
  8. 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
  9. 2024AMSNet: Netlist Dataset for AMS Circuitscited by 25
  10. 2024Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AIcited by 18

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 2; 2026: 5.

7 papers.

Similar, not cited

Close in wording, no citation either way

  1. 2026SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence
  2. 2026CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt
  3. 2025Graph Neural Networks Based Analog Circuit Link Prediction
  4. 2026SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence
  5. 2024AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAG
  6. 2025CIRCUIT: A Benchmark for Circuit Interpretation and Reasoning Capabilities of LLMs
  7. 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models
  8. 2025LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation