VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
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Abstract (arXiv)
Large Language Models (LLMs) have revolutionized code generation, achieving exceptional results on various established benchmarking frameworks. However, concerns about data contamination - where benchmark data inadvertently leaks into pre-training or fine-tuning datasets - raise questions about the validity of these evaluations. While this issue is known, limiting the industrial adoption of LLM-driven software engineering, hardware coding has received little to no attention regarding these risks. For the first time, we analyze state-of-the-art (SOTA) evaluation frameworks for Verilog code generation (VerilogEval and RTLLM), using established methods for contamination detection (CCD and Min-K% Prob). We cover SOTA commercial and open-source LLMs (CodeGen2.5, Minitron 4b, Mistral 7b, phi-4 mini, LLaMA-{1,2,3.1}, GPT-{2,3.5,4o}, Deepseek-Coder, and CodeQwen 1.5), in baseline and fine-tuned models (RTLCoder and Verigen). Our study confirms that data contamination is a critical concern. We explore mitigations and the resulting trade-offs for code quality vs fairness (i.e., reducing contamination toward unbiased benchmarking).
Key facts. Cited by 12 papers in the map (data through 14 Oct 2026). Builds on 44 of its 57 references that are in the map. First posted on arXiv 17 Mar 2025.
Builds on
44 of 57 references.
References · 44
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32 more
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Built on by
Citing papers per year: 2025: 6; 2026: 6.
12 papers.
- 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
- 2025NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestrationcited by 9
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
- 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimizationcited by 5
- 2025NotSoTiny: A Large, Living Benchmark for RTL Code Generationcited by 4
- 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
- 2026TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertioncited by 2
- 2025Breaking Memorization Barriers in LLM Code Fine-Tuning via Information Bottleneck for Improved Generalizationcited by 1
- 2026GUIDE: GenAI Units In Digital Design Educationcited by 1
- 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
- 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Modelscited by 0
- 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0
- 2026Hardware Design and Security in the Era of Chiplets and LLMs5 Aug 2026
- 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges11 May 2026
- 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models23 Apr 2026
- 2026GUIDE: GenAI Units In Digital Design Education18 Mar 2026
- 2026TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion23 Jan 2026
- 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation12 Jan 2026
- 2025NotSoTiny: A Large, Living Benchmark for RTL Code Generation23 Dec 2025
- 2025NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration27 Nov 2025
- 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization27 Nov 2025
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead29 Oct 2025
- 2025Breaking Memorization Barriers in LLM Code Fine-Tuning via Information Bottleneck for Improved Generalization15 Oct 2025
- 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design2 Jun 2025