mlsanityData to 7 Oct 2026

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework

arXiv 2501.02446 ↗First posted 5 Jan 2025cs.CR cs.AIcited by 3

On the map: LLM safety and security → Watermarking generated content and models

Abstract (arXiv)

Recent advances of large language models in the field of Verilog generation have raised several ethical and security concerns, such as code copyright protection and dissemination of malicious code. Researchers have employed watermarking techniques to identify codes generated by large language models. However, the existing watermarking works fail to protect RTL code copyright due to the significant syntactic and semantic differences between RTL code and software code in languages such as Python. This paper proposes a hardware watermarking framework RTLMarker that embeds watermarks into RTL code and deeper into the synthesized netlist. We propose a set of rule-based Verilog code transformations , ensuring the watermarked RTL code's syntactic and semantic correctness. In addition, we consider an inherent tradeoff between watermark transparency and watermark effectiveness and jointly optimize them. The results demonstrate RTLMarker's superiority over the baseline in RTL code watermarking.

Key facts. Cited by 3 papers in the map (data through 7 Oct 2026). Placed in Watermarking generated content and models, one of 12 directions in LLM safety and security. Builds on 9 of its 17 references that are in the map. First posted on arXiv 5 Jan 2025.

Builds on

9 of 17 references.

Closest ancestors · 1

Same direction, newest first

  1. 2023Who Wrote this Code? Watermarking for Code Generation24 May

Other references · 8

  1. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  2. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  3. 2020Adversarial Watermarking Transformer: Towards Tracing Text Provenance with Data Hidingcited by 121
  4. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
  5. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  6. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  7. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 69
  8. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36

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Cited by year

Citing papers per year: 2025: 3.

3 papers.

  1. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  2. 2025Robust and Secure Code Watermarking for Large Language Models via ML/Crypto Codesigncited by 0
  3. 2025RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Expertscited by 0