mlsanityData to 14 Oct 2026

HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databases

arXiv 2505.15701 ↗First posted 21 May 2025cs.AR cs.CL cs.LGcited by 1

On the map: Retrieval-augmented generation → RAG pipeline design and evaluation

Abstract (arXiv)

Retrieval Augmented Generation (RAG) is an essential agent for Large Language Model (LLM) aided Description Language (HDL) tasks, addressing the challenges of limited training data and prohibitively long prompts. However, its performance in handling ambiguous queries and real-world, repository-level HDL projects containing thousands or even tens of thousands of code lines remains limited. Our analysis demonstrates two fundamental mismatches, structural and vocabulary, between conventional semantic similarity-based RAGs and HDL codes. To this end, we propose HDLxGraph, the first framework that integrates the inherent graph characteristics of HDLs with RAGs for LLM-assisted tasks. Specifically, HDLxGraph incorporates Abstract Syntax Trees (ASTs) to capture HDLs' hierarchical structures and Data Flow Graphs (DFGs) to address the vocabulary mismatch. In addition, to overcome the lack of comprehensive HDL search benchmarks, we introduce HDLSearch, an LLM generated dataset derived from real-world, repository-level HDL projects. Evaluations show that HDLxGraph improves search, debugging, and completion accuracy by 12.04%/12.22%/5.04% and by 11.59%/8.18%/4.07% over state-of-the-art similarity-based RAG and software-code Graph RAG baselines, respectively. The code of HDLxGraph and HDLSearch benchmark are available at https://github.com/UMN-ZhaoLab/HDLxGraph.

Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Placed in RAG pipeline design and evaluation, one of 15 directions in Retrieval-augmented generation. Builds on 34 of its 48 references that are in the map. First posted on arXiv 21 May 2025.

Builds on

34 of 48 references.

Closest ancestors · 1

Same direction, newest first

  1. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA22 Jul

Other references · 33

  1. 2024The Llama 3 Herd of Modelscited by 14,715
  2. 2017Inductive Representation Learning on Large Graphscited by 6,320
  3. 2024From Local to Global: A Graph RAG Approach to Query-Focused Summarizationcited by 1,453
  4. 2024Qwen2.5-Coder Technical Reportcited by 1,203
  5. 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 885
  6. 2023Large Language Modelscited by 780
  7. 2024StarCoder 2 and The Stack v2: The Next Generationcited by 502
  8. 2023CodeT5+: Open Code Large Language Models for Code Understanding and Generationcited by 333
  9. 2024LightRAG: Simple and Fast Retrieval-Augmented Generationcited by 315
  10. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  11. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  12. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
21 more
  1. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  2. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  3. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  4. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
  5. 2024CodexGraph: Bridging Large Language Models and Code Repositories via Code Graph Databasescited by 65
  6. 2019Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integrationcited by 63
  7. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  8. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  9. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  10. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 26
  11. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 26
  12. 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
  13. 2023Fixing Hardware Security Bugs with Large Language Modelscited by 24
  14. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
  15. 2023LLM4DV: Using Large Language Models for Hardware Test Stimuli Generationcited by 23
  16. 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
  17. 2016A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devicescited by 17
  18. 2019The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technologycited by 17
  19. 2020A Toolkit for Generating Code Knowledge Graphscited by 17
  20. 2024Ask-EDA: A Design Assistant Empowered by LLM, Hybrid RAG and Abbreviation De-hallucinationcited by 14
  21. 2024CodeGRAG: Bridging the Gap between Natural Language and Programming Language via Graphical Retrieval Augmented Generationcited by 4

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Citing papers per year: 2026: 1.

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  6. 2024Graph Retrieval-Augmented Generation: A Survey
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