mlsanityData to 7 Oct 2026

PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices

arXiv 2608.26113 ↗First posted 28 May 2026cs.AIcited by 0

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Abstract (arXiv)

We present PICasso, an AI-assisted framework for automated synthesis, verification, and optimization of photonic integrated circuits (PICs) from natural-language specifications. PICasso couples a structured NL -> YAML -> GDS generation pipeline with PDK aware knowledge injection, automated placement and routing, DRC/LVS validation, and SAX-based photonic simulation. To systematically evaluate AI-driven photonic design, we introduce PIC-Set, a benchmark of 36 parameterized PIC design tasks spanning core photonic primitives and multi-component circuits. Using PIC-Set, we benchmark several state-of-the-art Large Language Models (LLMs) under a unified evaluation protocol, including new metrics such as structural and functional Spec@k, optimization efficiency, and robustness under perturbations. Across the benchmark, PICasso significantly improves end-to-end specification satisfaction compared to vanilla LLM generation. Structural Spec@3 reaches up to 92.7% and functional Spec@3 up to 52% on high-complexity circuits. In addition, PICasso consistently reduces circuit insertion loss, lowering the mean loss from 4.98 dB to 3.25 dB (1.74 dB improvement) through simulation-guided optimization. These results demonstrate that structured domain constraints, physical verification, and simulation feedback transform LLMs from brittle netlist generators into practical PIC design agents capable of producing manufacturable layouts with competitive runtimes relative to manual GUI-based workflows.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 21 of its 36 references that are in the map. First posted on arXiv 28 May 2026.

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References · 21

  1. 2022Why Can GPT Learn In-Context? Language Models Implicitly Perform Gradient Descent as Meta-Optimizerscited by 204
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  3. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  4. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  5. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
  6. 2023ChipGPT: How far are we from natural language hardware designcited by 101
  7. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
  8. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
  9. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
  10. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
  11. 2024AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 30
  12. 2024LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Designcited by 24
9 more
  1. 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
  2. 2024Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AIcited by 17
  3. 2024UVLLM: An Automated Universal RTL Verification Framework using LLMscited by 17
  4. 2024A Multi-Expert Large Language Model Architecture for Verilog Code Generationcited by 15
  5. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  6. 2025AI Agents for Photonic Integrated Circuit Design Automationcited by 7
  7. 2025PICBench: Benchmarking LLMs for Photonic Integrated Circuits Designcited by 5
  8. 2025LIMCA: LLM for Automating Analog In-Memory Computing Architecture Design Explorationcited by 4
  9. 2025TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generatorcited by 2

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