mlsanityData to 14 Oct 2026

HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design

arXiv 2412.05393 ↗First posted 6 Dec 2024cs.LG cs.AI cs.ARcited by 13

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Abstract (arXiv)

With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.

Key facts. Cited by 13 papers in the map (data through 14 Oct 2026). Builds on 14 of its 32 references that are in the map. First posted on arXiv 6 Dec 2024.

Builds on

14 of 32 references.

References · 14

  1. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  2. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  3. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  4. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 122
  5. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  6. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  7. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
  8. 2019Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integrationcited by 63
  9. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  10. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  11. 2020AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICscited by 26
  12. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
2 more
  1. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 15
  2. 2024SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generationcited by 9

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 6; 2026: 7.

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  1. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metriccited by 12
  2. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  3. 2025Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligencecited by 1
  4. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
  5. 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
  6. 2026VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designscited by 1
  7. 2026TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilogcited by 1
  8. 2026VeriPilot: An LLM-Powered Verilog Debugging Frameworkcited by 1
  9. 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestrationcited by 1
  10. 2026LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflowcited by 1
  11. 2025RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Expertscited by 0
  12. 2026LEGO: An LLM Skill-Based Front-End Design Generation Platformcited by 0
1 more
  1. 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0