mlsanityData to 14 Oct 2026

ChipNeMo: Domain-Adapted LLMs for Chip Design

arXiv 2311.00176 ↗First posted 31 Oct 2023cs.CLcited by 174

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Cited by 31 in LLM agents and tool use, but placed by its own abstract, which didn’t fit.

Abstract (arXiv)

ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we instead adopt the following domain adaptation techniques: domain-adaptive tokenization, domain-adaptive continued pretraining, model alignment with domain-specific instructions, and domain-adapted retrieval models. We evaluate these methods on three selected LLM applications for chip design: an engineering assistant chatbot, EDA script generation, and bug summarization and analysis. Our evaluations demonstrate that domain-adaptive pretraining of language models, can lead to superior performance in domain related downstream tasks compared to their base LLaMA2 counterparts, without degradations in generic capabilities. In particular, our largest model, ChipNeMo-70B, outperforms the highly capable GPT-4 on two of our use cases, namely engineering assistant chatbot and EDA scripts generation, while exhibiting competitive performance on bug summarization and analysis. These results underscore the potential of domain-specific customization for enhancing the effectiveness of large language models in specialized applications.

Key facts. Cited by 174 papers in the map (data through 14 Oct 2026). Builds on 48 of its 69 references that are in the map. First posted on arXiv 31 Oct 2023.

Builds on

48 of 69 references.

References · 48

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36 more
  1. 2021Finetuned Language Models Are Zero-Shot Learnerscited by 3,780
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Cited by year (2026 to 14 Oct)

Citing papers per year: 2023: 1; 2024: 64; 2025: 59; 2026: 50.

174 papers.

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  1. 2024Tower: An Open Multilingual Large Language Model for Translation-Related Taskscited by 206
  2. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
  3. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 84
  4. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  5. 2024WirelessLLM: Empowering Large Language Models Towards Wireless Intelligencecited by 44
  6. 2024ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Modelscited by 44
  7. 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 43
  8. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
  9. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  10. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  11. 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 37
  12. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
38 more
  1. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  2. 2024MoRA: High-Rank Updating for Parameter-Efficient Fine-Tuningcited by 31
  3. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 31
  4. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
  5. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
  6. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 26
  7. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 26
  8. 2024Large Language Models for Manufacturingcited by 24
  9. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  10. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 20
  11. 2025OmniScience: A Domain-Specialized LLM for Scientific Reasoning and Discoverycited by 20
  12. 2024CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generationcited by 19
  13. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 19
  14. 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
  15. 2024AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Modelscited by 18
  16. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
  17. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  18. 2025SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoningcited by 16
  19. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  20. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 15
  21. 2024FACTS About Building Retrieval Augmented Generation-based Chatbotscited by 15
  22. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
  23. 2024Blox-Net: Generative Design-for-Robot-Assembly Using VLM Supervision, Physics Simulation, and a Robot with Resetcited by 15
  24. 2024ESPACE: Dimensionality Reduction of Activations for Model Compressioncited by 15
  25. 2024EEE-Bench: A Comprehensive Multimodal Electrical And Electronics Engineering Benchmarkcited by 15
  26. 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 15
  27. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 15
  28. 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
  29. 2024Ask-EDA: A Design Assistant Empowered by LLM, Hybrid RAG and Abbreviation De-hallucinationcited by 14
  30. 2025ORFS-agent: Tool-Using Agents for Chip Design Optimizationcited by 14
  31. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  32. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 13
  33. 2024LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generationcited by 13
  34. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 13
  35. 2025Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automationcited by 12
  36. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  37. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
  38. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMscited by 12

50 most cited of 174 All 174 (JSON)

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  1. 2024ChipExpert: The Open-Source Integrated-Circuit-Design-Specific Large Language Model
  2. 2026iScript: A Domain-Adapted Large Language Model and Benchmark for Physical Design Tcl Script Generation
  3. 2025Large Language Models (LLMs) for Electronic Design Automation (EDA)
  4. 2026A Generalizable Framework for Building Executable Domain-Specific LLMs under Data Scarcity: Demonstration on Semiconductor TCAD Simulation
  5. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  6. 2025Enhancing Reasoning to Adapt Large Language Models for Domain-Specific Applications
  7. 2024Fine-tuning large language models for domain adaptation: Exploration of training strategies, scaling, model merging and synergistic capabilities
  8. 2025Towards LLM-based Root Cause Analysis of Hardware Design Failures