mlsanityData to 14 Oct 2026

QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generation

arXiv 2602.00704 ↗First posted 31 Jan 2026cs.LGcited by 1

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Abstract (arXiv)

The generation of Register-Transfer Level (RTL) code is a crucial yet labor-intensive step in digital hardware design, traditionally requiring engineers to manually translate complex specifications into thousands of lines of synthesizable Hardware Description Language (HDL) code. While Large Language Models (LLMs) have shown promise in automating this process, existing approaches--including fine-tuned domain-specific models and advanced agent-based systems--struggle to scale to industrial IP-level design tasks. We identify three key challenges: (1) handling long, highly detailed documents, where critical interface constraints become buried in unrelated submodule descriptions; (2) generating long RTL code, where both syntactic and semantic correctness degrade sharply with increasing output length; and (3) navigating the complex debugging cycles required for functional verification through simulation and waveform analysis. To overcome these challenges, we propose ChipV-RTL, a multi-agent framework that leverages information locality in modular hardware design. ChipV-RTL decomposes the long-document to long-code generation problem into a set of short-document, short-code tasks, enabling scalable generation and debugging. Specifically, ChipV-RTL integrates hierarchical document partitioning, task planning, localized code generation, interface-consistent merging, and AST-guided locality-aware debugging. Experiments on RealBench, an IP-level Verilog generation benchmark, demonstrate that ChipV-RTL substantially outperforms state-of-the-art (SOTA) LLMs and agents, achieving a pass rate of 45.0% compared to 21.6%. Code, project page are available at https://iprc-dip.github.io/ChipV-RTL/.

Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 21 of its 30 references that are in the map. First posted on arXiv 31 Jan 2026.

Builds on

21 of 30 references.

References · 21

  1. 2025Qwen3 Technical Reportcited by 8,820
  2. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  3. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  4. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  5. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  6. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  7. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  8. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
  9. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  10. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  11. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 44
  12. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
9 more
  1. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  2. 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generationcited by 35
  3. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
  4. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  5. 2025Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systemscited by 18
  6. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  7. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  8. 2025DeepRTL2: A Versatile Model for RTL-Related Taskscited by 10
  9. 2025RTLSquad: Multi-Agent Based Interpretable RTL Designcited by 9

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 1.

1 paper.

  1. 2026Exploring the Agentic Frontier of Verilog Code Generationcited by 1