mlsanityData to 7 Oct 2026

RTLRewriter: Methodologies for Large Models aided RTL Code Optimization

arXiv 2409.11414 ↗First posted 4 Sep 2024cs.AR cs.AI cs.SEcited by 30

Not on the map. Why?

Abstract (arXiv)

Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and performance of digital circuits during early synthesis stages. Currently, optimization relies heavily on manual efforts by skilled engineers, often requiring multiple iterations based on synthesis feedback. In contrast, existing compiler-based methods fall short in addressing complex designs. This paper introduces RTLRewriter, an innovative framework that leverages large models to optimize RTL code. A circuit partition pipeline is utilized for fast synthesis and efficient rewriting. A multi-modal program analysis is proposed to incorporate vital visual diagram information as optimization cues. A specialized search engine is designed to identify useful optimization guides, algorithms, and code snippets that enhance the model ability to generate optimized RTL. Additionally, we introduce a Cost-aware Monte Carlo Tree Search (C-MCTS) algorithm for efficient rewriting, managing diverse retrieved contents and steering the rewriting results. Furthermore, a fast verification pipeline is proposed to reduce verification cost. To cater to the needs of both industry and academia, we propose two benchmarking suites: the Large Rewriter Benchmark, targeting complex scenarios with extensive circuit partitioning, optimization trade-offs, and verification challenges, and the Small Rewriter Benchmark, designed for a wider range of scenarios and patterns. Our comparative analysis with established compilers such as Yosys and E-graph demonstrates significant improvements, highlighting the benefits of integrating large models into the early stages of circuit design. We provide our benchmarks at https://github.com/yaoxufeng/RTLRewriter-Bench.

Key facts. Cited by 30 papers in the map (data through 7 Oct 2026). Builds on 20 of its 62 references that are in the map. First posted on arXiv 4 Sep 2024.

Builds on

20 of 62 references.

References · 20

  1. 2020An Image is Worth 16x16 Words: Transformers for Image Recognition at Scalecited by 29,915
  2. 2023GPT-4 Technical Reportcited by 18,132
  3. 2023Llama 2: Open Foundation and Fine-Tuned Chat Modelscited by 12,865
  4. 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,302
  5. 2016XGBoost: A Scalable Tree Boosting Systemcited by 5,120
  6. 2023Lost in the Middle: How Language Models Use Long Contextscited by 3,383
  7. 2024DeepSeek LLM: Scaling Open-Source Language Models with Longtermismcited by 621
  8. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
  9. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  10. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  11. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
  12. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
8 more
  1. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  2. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  3. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 69
  4. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
  5. 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 42
  6. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
  7. 2023A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Designcited by 6
  8. 2024Logic Synthesis with Generative Deep Neural Networkscited by 4

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2024: 1; 2025: 20; 2026: 9.

30 papers.

Sort:

By area:

  1. 2025A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDAcited by 17
  2. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  3. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
  4. 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
  5. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  6. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMscited by 7
  7. 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
  8. 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflectioncited by 5
  9. 2025ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learningcited by 5
  10. 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMscited by 4
  11. 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learningcited by 3
  12. 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Codecited by 3
18 more
  1. 2025CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMscited by 3
  2. 2025Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Codecited by 3
  3. 2025SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chipcited by 2
  4. 2025AgenticTCAD: A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimizationcited by 2
  5. 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimizationcited by 2
  6. 2025BRIDGES: Bridging Graph Modality and Large Language Models within EDA Taskscited by 1
  7. 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
  8. 2025Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosiscited by 1
  9. 2025Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaborationcited by 1
  10. 2025CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systemscited by 1
  11. 2025GENIAL: Generative Design Space Exploration via Network Inversion for Low Power Algorithmic Logic Unitscited by 0
  12. 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learningcited by 0
  13. 2026Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generationcited by 0
  14. 2026LLM4RTL: Tool-Assisted LLM for RTL Generationcited by 0
  15. 2026AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewritingcited by 0
  16. 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestrationcited by 0
  17. 2026TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agentscited by 0
  18. 2026ChipMEM: Verification-Grounded Memory for EDA Agentscited by 0