mlsanityData to 14 Oct 2026

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation

arXiv 2507.13369 ↗First posted 9 Jul 2025cs.AR cs.AI cs.LGcited by 8

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Abstract (arXiv)

Large Language Models (LLMs) are gaining popularity for hardware design automation, particularly through Register Transfer Level (RTL) code generation. In this work, we examine the current literature on RTL generation using LLMs and identify key requirements for training and fine-tuning datasets. We construct a robust Verilog dataset through an automated three-pronged process involving database (DB) creation and management with PostgreSQL, data collection from code hosting sites like OpenCores and GitHub, and data preprocessing to verify the codes' syntax, run logic synthesis, and extract relevant module metadata. We implement a scalable and efficient DB infrastructure to support analysis and detail our preprocessing pipeline to enforce high-quality data before DB insertion. The resulting dataset comprises 20,392 Verilog samples, 751 MB of Verilog code data, which is the largest high-quality Verilog dataset for LLM fine-tuning to our knowledge. We further evaluate the dataset, address associated challenges, and explore potential applications for future research and development in LLM-based hardware generation.

Key facts. Cited by 8 papers in the map (data through 14 Oct 2026). Builds on 32 of its 55 references that are in the map. First posted on arXiv 9 Jul 2025.

Builds on

32 of 55 references.

References · 32

  1. 2023Retrieval-Augmented Generation for Large Language Models: A Surveycited by 2,212
  2. 2023Code Llama: Open Foundation Models for Codecited by 2,139
  3. 2019Class-Balanced Loss Based on Effective Number of Samplescited by 1,245
  4. 2021Deduplicating Training Data Makes Language Models Bettercited by 714
  5. 2024A Systematic Survey of Prompt Engineering in Large Language Models: Techniques and Applicationscited by 431
  6. 2022UniXcoder: Unified Cross-Modal Pre-training for Code Representationcited by 361
  7. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  8. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  9. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  10. 2024The Prompt Report: A Systematic Survey of Prompt Engineering Techniquescited by 121
  11. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  12. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
20 more
  1. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  2. 2021Machine Learning for Electronic Design Automation: A Surveycited by 72
  3. 2024Retrieval-Augmented Generation for Natural Language Processing: A Surveycited by 71
  4. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  5. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  6. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 41
  7. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  8. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  9. 2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 31
  10. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 26
  11. 2023LLM4DV: Using Large Language Models for Hardware Test Stimuli Generationcited by 23
  12. 2023LLM for SoC Security: A Paradigm Shiftcited by 22
  13. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
  14. 2024Code Needs Comments: Enhancing Code LLMs with Comment Augmentationcited by 16
  15. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  16. 2025Intrinsic Entropy of Context Length Scaling in LLMscited by 14
  17. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  18. 2024CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generationcited by 9
  19. 2025ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verificationcited by 7
  20. 2024Extending Context Window of Large Language Models from a Distributional Perspectivecited by 6

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 4; 2026: 4.

8 papers.

  1. 2025Retrieval-Augmented Code Generation: A Survey with Focus on Repository-Level Approachescited by 23
  2. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  3. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
  4. 2026LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflowcited by 1
  5. 2025Mitigating hallucinations and omissions in LLMs for invertible problems: An application to hardware logic design automationcited by 0
  6. 2026ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verificationcited by 0
  7. 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Modelscited by 0
  8. 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0