mlsanityData to 14 Oct 2026

LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation

arXiv 2401.12224 ↗First posted 28 Dec 2023cs.AR cs.AIcited by 40

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Abstract (arXiv)

Driven by Moore's Law, the complexity and scale of modern chip design are increasing rapidly. Electronic Design Automation (EDA) has been widely applied to address the challenges encountered in the full chip design process. However, the evolution of very large-scale integrated circuits has made chip design time-consuming and resource-intensive, requiring substantial prior expert knowledge. Additionally, intermediate human control activities are crucial for seeking optimal solutions. In system design stage, circuits are usually represented with Hardware Description Language (HDL) as a textual format. Recently, Large Language Models (LLMs) have demonstrated their capability in context understanding, logic reasoning and answer generation. Since circuit can be represented with HDL in a textual format, it is reasonable to question whether LLMs can be leveraged in the EDA field to achieve fully automated chip design and generate circuits with improved power, performance, and area (PPA). In this paper, we present a systematic study on the application of LLMs in the EDA field, categorizing it into the following cases: 1) assistant chatbot, 2) HDL and script generation, and 3) HDL verification and analysis. Additionally, we highlight the future research direction, focusing on applying LLMs in logic synthesis, physical design, multi-modal feature extraction and alignment of circuits. We collect relevant papers up-to-date in this field via the following link: https://github.com/Thinklab-SJTU/Awesome-LLM4EDA.

Key facts. Cited by 40 papers in the map (data through 14 Oct 2026). Builds on 40 of its 62 references that are in the map. First posted on arXiv 28 Dec 2023.

Builds on

40 of 62 references.

References · 40

  1. 2021Learning Transferable Visual Models From Natural Language Supervisioncited by 33,744
  2. 2020Language Models are Few-Shot Learnerscited by 32,419
  3. 2022Training language models to follow instructions with human feedbackcited by 15,971
  4. 2023LLaMA: Open and Efficient Foundation Language Modelscited by 14,132
  5. 2020Retrieval-Augmented Generation for Knowledge-Intensive NLP Taskscited by 9,297
  6. 2022ReAct: Synergizing Reasoning and Acting in Language Modelscited by 8,695
  7. 2017Deep reinforcement learning from human preferencescited by 3,912
  8. 2020Learning to summarize from human feedbackcited by 2,588
  9. 2022Survey of Hallucination in Natural Language Generationcited by 2,075
  10. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  11. 2023GraphGPT: Graph Instruction Tuning for Large Language Modelscited by 226
  12. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
28 more
  1. 2023An Empirical Evaluation of Using Large Language Models for Automated Unit Test Generationcited by 194
  2. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  3. 2023Large-scale Multi-Modal Pre-trained Models: A Comprehensive Surveycited by 153
  4. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  5. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  6. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 122
  7. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  8. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  9. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  10. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  11. 2023Review of Large Vision Models and Visual Prompt Engineeringcited by 77
  12. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  13. 2019Hybrid Actor-Critic Reinforcement Learning in Parameterized Action Spacecited by 54
  14. 2019DRiLLS: Deep Reinforcement Learning for Logic Synthesiscited by 47
  15. 2021On Joint Learning for Solving Placement and Routing in Chip Designcited by 44
  16. 2022MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learningcited by 43
  17. 2021DeepGate: Learning Neural Representations of Logic Gatescited by 37
  18. 2023DeepGate2: Functionality-Aware Circuit Representation Learningcited by 33
  19. 2023(Security) Assertions by Large Language Modelscited by 32
  20. 2023Fixing Hardware Security Bugs with Large Language Modelscited by 24
  21. 2023The Power of Large Language Models for Wireless Communication System Development: A Case Study on FPGA Platformscited by 20
  22. 2021BOiLS: Bayesian Optimisation for Logic Synthesiscited by 18
  23. 2023Using LLMs to Facilitate Formal Verification of RTLcited by 18
  24. 2021AutoSVA: Democratizing Formal Verification of RTL Module Interactionscited by 12
  25. 2023DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protectioncited by 12
  26. 2023A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automationcited by 10
  27. 2023Unlocking Hardware Security Assurance: The Potential of LLMscited by 9
  28. 2023New Interaction Paradigm for Complex EDA Software Leveraging GPTcited by 4

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2024: 12; 2025: 18; 2026: 10.

40 papers.

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  1. 2024ToolACE: Winning the Points of LLM Function Callingcited by 216
  2. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
  3. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 84
  4. 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 37
  5. 2024CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generationcited by 19
  6. 2024AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAGcited by 16
  7. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  8. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 15
  9. 2024APEX: An Extensible and Dynamism-Aware Simulator for Automated Parallel Execution in LLM Servingcited by 15
  10. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 15
  11. 2024Enhancing Function-Calling Capabilities in LLMs: Strategies for Prompt Formats, Data Integration, and Multilingual Translationcited by 14
  12. 2025ORFS-agent: Tool-Using Agents for Chip Design Optimizationcited by 14
28 more
  1. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 13
  2. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 13
  3. 2025Failure Makes the Agent Stronger: Enhancing Accuracy through Structured Reflection for Reliable Tool Interactionscited by 12
  4. 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
  5. 2024New Solutions on LLM Acceleration, Optimization, and Applicationcited by 7
  6. 2024SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detectioncited by 7
  7. 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMscited by 7
  8. 2025AI Agents for Photonic Integrated Circuit Design Automationcited by 7
  9. 2025Self-Guided Function Calling in Large Language Models via Stepwise Experience Recallcited by 7
  10. 2025AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agentscited by 6
  11. 2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Modelscited by 4
  12. 2025Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMscited by 2
  13. 2025SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chipcited by 2
  14. 2025EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Codecited by 2
  15. 2026QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesiscited by 2
  16. 2026DRCY: Agentic Hardware Design Reviewscited by 2
  17. 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMscited by 2
  18. 2024IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDAcited by 1
  19. 2025Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaborationcited by 1
  20. 2026AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrievalcited by 1
  21. 2026GenesisFunc: Multi-Agent Data Generation for Accurate and Generalizable Function-Callingcited by 1
  22. 2026AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuitscited by 1
  23. 2025D2S-FLOW: Automated Parameter Extraction from Datasheets for SPICE Model Generation Using Large Language Modelscited by 0
  24. 2025Deep Representation Learning for Electronic Design Automationcited by 0
  25. 2026Complexity Horizons of Compressed Models in Analog Circuit Analysiscited by 0
  26. 2026When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answeringcited by 0
  27. 2026Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflowscited by 0
  28. 2026SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedbackcited by 0