AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs
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Abstract (arXiv)
Despite recent advances, analog front-end design still relies heavily on expert intuition and iterative simulations, which limits the potential for automation. We present AnalogCoder-Pro, a multimodal large language model (LLM) framework that integrates generative and optimization techniques. The framework features a multimodal diagnosis-and-repair feedback loop that uses simulation error messages and waveform images to autonomously correct design errors. It also builds a reusable circuit tool library by archiving successful designs as modular subcircuits, accelerating the development of complex systems. Furthermore, it enables end-to-end automation by generating circuit topologies from target specifications, extracting key parameters, and applying Bayesian optimization for device sizing. On a curated benchmark suite covering 13 circuit types, AnalogCoder-Pro successfully designed 28 circuits and consistently outperformed existing LLM-based methods in figures of merit.
Key facts. Cited by 14 papers in the map (data through 7 Oct 2026). Builds on 49 of its 87 references that are in the map. First posted on arXiv 4 Aug 2025.
Builds on
49 of 87 references.
References · 49
- 2021LoRA: Low-Rank Adaptation of Large Language Modelscited by 14,084
- 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,302
- 2019Optuna: A Next-generation Hyperparameter Optimization Frameworkcited by 2,455
- 2023Voyager: An Open-Ended Embodied Agent with Large Language Modelscited by 2,081
- 2023ToolLLM: Facilitating Large Language Models to Master 16000+ Real-world APIscited by 1,880
- 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,154
- 2023CodeGeeX: A Pre-Trained Model for Code Generation with Multilingual Benchmarking on HumanEval-Xcited by 294
- 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
- 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
- 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
- 2023ChipGPT: How far are we from natural language hardware designcited by 101
37 more
- 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
- 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
- 2020GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learningcited by 89
- 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
- 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
- 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
- 2023CktGNN: Circuit Graph Neural Network for Electronic Design Automationcited by 55
- 2020AutoCkt: Deep Reinforcement Learning of Analog Circuit Designscited by 51
- 2024ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Modelscited by 44
- 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 41
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
- 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
- 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 35
- 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generationcited by 34
- 2024LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuitscited by 32
- 2024AmpAgent: An LLM-based Multi-Agent System for Multi-stage Amplifier Schematic Design from Literature for Process and Performance Portingcited by 29
- 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
- 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 25
- 2024LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuitscited by 22
- 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
- 2021DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networkscited by 18
- 2024Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AIcited by 17
- 2024AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Modelscited by 17
- 2025A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDAcited by 17
- 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 16
- 2025CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Designcited by 14
- 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuitscited by 14
- 2025Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automationcited by 12
- 2024LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generationcited by 11
- 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
- 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
- 2025AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generationcited by 10
- 2024INSIGHT: Universal Neural Simulator for Analog Circuits Harnessing Autoregressive Transformerscited by 8
- 2025LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generationcited by 6
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
- 2025Evaluating LLM-based Workflows for Switched-Mode Power Supply Designcited by 2
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Citing papers per year: 2025: 3; 2026: 11.
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- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimizationcited by 5
- 2026AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agentscited by 4
- 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generationcited by 2
- 2026CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Promptcited by 2
- 2025Dataset Construction for Training LLM to Learn Analog Circuit Knowledgecited by 1
- 2025Combining Large Language Models and Gradient-Free Optimization for Automatic Control Policy Synthesiscited by 1
- 2026PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converterscited by 1
- 2026AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learningcited by 1
- 2026SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flowscited by 1
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Modelscited by 0
- 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Modelscited by 0
- 2026Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Tasks27 Sep 2026
- 2026EngIntervene: Benchmarking Multimodal Engineering State Understanding and Design Intervention Reasoning27 Sep 2026
- 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models13 Aug 2026
- 2026EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models15 Jul 2026
- 2026SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows4 Jul 2026
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2026CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt7 May 2026
- 2026AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learning12 Feb 2026
- 2026AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agents2 Feb 2026
- 2026PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converters29 Jan 2026
- 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation27 Jan 2026
- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization24 Nov 2025
- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimizationcited by 5
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Taskscited by 0
- 2026Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Tasks27 Sep 2026
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization24 Nov 2025
- 2026AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agentscited by 4
- 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generationcited by 2
- 2026CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Promptcited by 2
- 2025Dataset Construction for Training LLM to Learn Analog Circuit Knowledgecited by 1
- 2025Combining Large Language Models and Gradient-Free Optimization for Automatic Control Policy Synthesiscited by 1
- 2026PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converterscited by 1
- 2026AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learningcited by 1
- 2026SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flowscited by 1
- 2026EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Modelscited by 0
- 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Modelscited by 0
- 2026EngIntervene: Benchmarking Multimodal Engineering State Understanding and Design Intervention Reasoningcited by 0
- 2026EngIntervene: Benchmarking Multimodal Engineering State Understanding and Design Intervention Reasoning27 Sep 2026
- 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models13 Aug 2026
- 2026EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models15 Jul 2026
- 2026SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows4 Jul 2026
- 2026CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt7 May 2026
- 2026AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learning12 Feb 2026
- 2026AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agents2 Feb 2026
- 2026PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converters29 Jan 2026
- 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation27 Jan 2026
- 2025Combining Large Language Models and Gradient-Free Optimization for Automatic Control Policy Synthesis1 Oct 2025
- 2025Dataset Construction for Training LLM to Learn Analog Circuit Knowledge14 Aug 2025
Similar, not cited
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- 2026AnalogAgent: Self-Improving Analog Circuit Design Automation with LLM Agents
- 2024CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence
- 2025White-Box Reasoning: Synergizing LLM Strategy and gm/Id Data for Automated Analog Circuit Design
- 2025EEschematic: Multimodal-LLM Based AI Agent for Schematic Generation of Analog Circuit
- 2025AnalogSAGE: Self-evolving Analog Design Multi-Agents with Stratified Memory and Grounded Experience
- 2025CIRCUIT: A Benchmark for Circuit Interpretation and Reasoning Capabilities of LLMs
- 2026Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement
- 2026AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing