A Survey of Research in Large Language Models for Electronic Design Automation
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Abstract (arXiv)
Within the rapidly evolving domain of Electronic Design Automation (EDA), Large Language Models (LLMs) have emerged as transformative technologies, offering unprecedented capabilities for optimizing and automating various aspects of electronic design. This survey provides a comprehensive exploration of LLM applications in EDA, focusing on advancements in model architectures, the implications of varying model sizes, and innovative customization techniques that enable tailored analytical insights. By examining the intersection of LLM capabilities and EDA requirements, the paper highlights the significant impact these models have on extracting nuanced understandings from complex datasets. Furthermore, it addresses the challenges and opportunities in integrating LLMs into EDA workflows, paving the way for future research and application in this dynamic field. Through this detailed analysis, the survey aims to offer valuable insights to professionals in the EDA industry, AI researchers, and anyone interested in the convergence of advanced AI technologies and electronic design.
Key facts. Cited by 38 papers in the map (data through 7 Oct 2026). Builds on 44 of its 64 references that are in the map. First posted on arXiv 16 Jan 2025.
Builds on
44 of 64 references.
References · 44
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- 2020Language Models are Few-Shot Learnerscited by 32,199
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- 2021Zero-Shot Text-to-Image Generationcited by 4,276
- 2017Deep reinforcement learning from human preferencescited by 3,846
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32 more
- 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,154
- 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 876
- 2023Learning to Compress Prompts with Gist Tokenscited by 379
- 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
- 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
- 2023An Empirical Evaluation of Using Large Language Models for Automated Unit Test Generationcited by 193
- 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
- 2024CodeGemma: Open Code Models Based on Gemmacited by 145
- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
- 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 118
- 2023ChipGPT: How far are we from natural language hardware designcited by 101
- 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
- 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
- 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
- 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 82
- 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
- 2023Reinforcement Learning with Human Feedback: Learning Dynamic Choices via Pessimismcited by 69
- 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 69
- 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 42
- 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
- 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
- 2024LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Designcited by 24
- 2024The Price of Prompting: Profiling Energy Use in Large Language Models Inferencecited by 22
- 2023The Power of Large Language Models for Wireless Communication System Development: A Case Study on FPGA Platformscited by 20
- 2024LLoCO: Learning Long Contexts Offlinecited by 16
- 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 16
- 2024DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agentcited by 15
- 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 12
- 2023On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Acceleratorscited by 11
- 2024LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generationcited by 11
- 2023A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automationcited by 10
- 2024Large Language Model (LLM) for Standard Cell Layout Design Optimizationcited by 9
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Citing papers per year: 2025: 13; 2026: 25.
38 papers.
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- 2025LoopTool: Closing the Data-Training Loop for Robust LLM Tool Callscited by 16
- 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuitscited by 14
- 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
- 2026POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimizationcited by 11
- 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 8
- 2025AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agentscited by 6
- 2026HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Taskscited by 6
- 2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvementcited by 5
- 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoningcited by 4
- 2026CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Promptscited by 4
26 more
- 2025CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMscited by 3
- 2025NotSoTiny: A Large, Living Benchmark for RTL Code Generationcited by 3
- 2026Automated QoR improvement in OpenROAD with coding agentscited by 3
- 2026CktEvo: Repository-Level RTL Code Benchmark for Design Evolutioncited by 3
- 2025EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generationcited by 2
- 2026Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generationcited by 2
- 2026Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Developmentcited by 2
- 2025ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocolscited by 1
- 2025AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testingcited by 1
- 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMscited by 1
- 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learningcited by 0
- 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Modelscited by 0
- 2026RuC: HDL-Agnostic Rule Completion Benchmark Generationcited by 0
- 2026From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generationcited by 0
- 2026Complexity Horizons of Compressed Models in Analog Circuit Analysiscited by 0
- 2026OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Designcited by 0
- 2026Surveying GenAI-based Automation in Printed Circuit Board Design and Testcited by 0
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026An LLM-Orchestrated Agent for Directional-Coupler Design with Self-Consistent Eigenmode and FDTD Validationcited by 0
- 2026When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answeringcited by 0
- 2026PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generationcited by 0
- 2026VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Spacecited by 0
- 2026SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedbackcited by 0
- 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestrationcited by 0
- 2026Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systemscited by 0
- 2026Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Taskscited by 0
- 2026Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Tasks27 Sep 2026
- 2026Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems28 Aug 2026
- 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration27 Aug 2026
- 2026SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedback9 Aug 2026
- 2026VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space3 Aug 2026
- 2026PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation3 Aug 2026
- 2026When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering19 Jul 2026
- 2026An LLM-Orchestrated Agent for Directional-Coupler Design with Self-Consistent Eigenmode and FDTD Validation21 Jun 2026
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2026Surveying GenAI-based Automation in Printed Circuit Board Design and Test10 Jun 2026
- 2026OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design9 Jun 2026
- 2026Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Development19 May 2026
26 more
- 2026Complexity Horizons of Compressed Models in Analog Circuit Analysis4 May 2026
- 2026From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation30 Apr 2026
- 2026RuC: HDL-Agnostic Rule Completion Benchmark Generation30 Apr 2026
- 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs30 Apr 2026
- 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models23 Apr 2026
- 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning20 Apr 2026
- 2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement16 Apr 2026
- 2026HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Tasks16 Apr 2026
- 2026POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimization19 Mar 2026
- 2026CktEvo: Repository-Level RTL Code Benchmark for Design Evolution10 Feb 2026
- 2026Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation16 Jan 2026
- 2026Automated QoR improvement in OpenROAD with coding agents9 Jan 2026
- 2026CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts8 Jan 2026
- 2025NotSoTiny: A Large, Living Benchmark for RTL Code Generation23 Dec 2025
- 2025AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testing12 Dec 2025
- 2025EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation15 Nov 2025
- 2025LoopTool: Closing the Data-Training Loop for Robust LLM Tool Calls12 Nov 2025
- 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning4 Nov 2025
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Design5 Sep 2025
- 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs4 Aug 2025
- 2025AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agents1 Aug 2025
- 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization25 Jul 2025
- 2025CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs2 Jul 2025
- 2025ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols9 Jun 2025
- 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuits30 May 2025
- 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generation31 Mar 2025
- 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
- 2025AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agentscited by 6
- 2026HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Taskscited by 6
- 2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvementcited by 5
- 2026CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Promptscited by 4
- 2026Automated QoR improvement in OpenROAD with coding agentscited by 3
- 2026Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Developmentcited by 2
- 2025AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testingcited by 1
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generationcited by 0
- 2026VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Spacecited by 0
- 2026SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedbackcited by 0
12 most cited of 13 All 13 (JSON)
- 2026Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Tasks27 Sep 2026
- 2026SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedback9 Aug 2026
- 2026VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space3 Aug 2026
- 2026PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation3 Aug 2026
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2026Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Development19 May 2026
- 2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement16 Apr 2026
- 2026HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Tasks16 Apr 2026
- 2026Automated QoR improvement in OpenROAD with coding agents9 Jan 2026
- 2026CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts8 Jan 2026
- 2025AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testing12 Dec 2025
- 2025AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agents1 Aug 2025
12 newest of 13 All 13 (JSON)
- 2025LoopTool: Closing the Data-Training Loop for Robust LLM Tool Callscited by 16
- 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuitscited by 14
- 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
- 2026POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimizationcited by 11
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 8
- 2025CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMscited by 3
- 2025NotSoTiny: A Large, Living Benchmark for RTL Code Generationcited by 3
- 2026CktEvo: Repository-Level RTL Code Benchmark for Design Evolutioncited by 3
- 2025EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generationcited by 2
- 2026Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generationcited by 2
- 2025ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocolscited by 1
12 most cited of 23 All 23 (JSON)
- 2026Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems28 Aug 2026
- 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration27 Aug 2026
- 2026When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering19 Jul 2026
- 2026An LLM-Orchestrated Agent for Directional-Coupler Design with Self-Consistent Eigenmode and FDTD Validation21 Jun 2026
- 2026Surveying GenAI-based Automation in Printed Circuit Board Design and Test10 Jun 2026
- 2026OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design9 Jun 2026
- 2026Complexity Horizons of Compressed Models in Analog Circuit Analysis4 May 2026
- 2026RuC: HDL-Agnostic Rule Completion Benchmark Generation30 Apr 2026
- 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs30 Apr 2026
- 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models23 Apr 2026
- 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning20 Apr 2026
- 2026POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimization19 Mar 2026
12 newest of 23 All 23 (JSON)