mlsanityData to 14 Oct 2026

Large Language Models (LLMs) for Electronic Design Automation (EDA)

arXiv 2508.20030 ↗First posted 27 Aug 2025eess.SY cs.AI cs.ARcited by 3

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Abstract (arXiv)

With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufacturing workflow. This workflow involves numerous iterations, making it both labor-intensive and error-prone. Therefore, there is an urgent demand for more efficient Electronic Design Automation (EDA) solutions to accelerate hardware development. Recently, large language models (LLMs) have shown remarkable advancements in contextual comprehension, logical reasoning, and generative capabilities. Since hardware designs and intermediate scripts can be represented as text, integrating LLM for EDA offers a promising opportunity to simplify and even automate the entire workflow. Accordingly, this paper provides a comprehensive overview of incorporating LLMs into EDA, with emphasis on their capabilities, limitations, and future opportunities. Three case studies, along with their outlook, are introduced to demonstrate the capabilities of LLMs in hardware design, testing, and optimization. Finally, future directions and challenges are highlighted to further explore the potential of LLMs in shaping the next-generation EDA, providing valuable insights for researchers interested in leveraging advanced AI technologies for EDA.

Key facts. Cited by 3 papers in the map (data through 14 Oct 2026). Builds on 30 of its 47 references that are in the map. First posted on arXiv 27 Aug 2025.

Builds on

30 of 47 references.

References · 30

  1. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  2. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  3. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  4. 2023Structured Chain-of-Thought Prompting for Code Generationcited by 138
  5. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  6. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  7. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  8. 2020DAVE: Deriving Automatically Verilog from Englishcited by 48
  9. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 41
  10. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  11. 2024AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
  12. 2024Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAcited by 28
18 more
  1. 2024LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Designcited by 25
  2. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
  3. 2024CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Designcited by 24
  4. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 20
  5. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 19
  6. 2023Using LLMs to Facilitate Formal Verification of RTLcited by 18
  7. 2024Automated C/C++ Program Repair for High-Level Synthesis via Large Language Modelscited by 18
  8. 2024C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gapcited by 16
  9. 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 15
  10. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
  11. 2024LLM-Aided Efficient Hardware Design Automationcited by 11
  12. 2025VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistencycited by 11
  13. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
  14. 2024SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Modelcited by 9
  15. 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
  16. 2024Evaluating LLMs for Hardware Design and Testcited by 8
  17. 2024New Solutions on LLM Acceleration, Optimization, and Applicationcited by 7
  18. 2023Logic Design of Neural Networks for High-Throughput and Low-Power Applicationscited by 4

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 3.

3 papers.

  1. 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
  2. 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestrationcited by 1
  3. 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026LLM for EDA in Front-End Design: Challenges and Opportunities
  2. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDA
  3. 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs
  4. 2025AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agents
  5. 2025JARVIS: A Multi-Agent Code Assistant for High-Quality EDA Script Generation
  6. 2025Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation
  7. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
  8. 2026CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts