mlsanityData to 14 Oct 2026

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization

arXiv 2507.19570 ↗First posted 25 Jul 2025cs.AR cs.MAcited by 9

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

This paper presents MCP4EDA, the first Model Context Protocol server that enables Large Language Models (LLMs) to control and optimize the complete open-source RTL-to-GDSII design flow through natural language interaction. The system integrates Yosys synthesis, Icarus Verilog simulation, OpenLane place-and-route, GTKWave analysis, and KLayout visualization into a unified LLM-accessible interface, enabling designers to execute complex multi-tool EDA workflows conversationally via AI assistants such as Claude Desktop and Cursor IDE. The principal contribution is a backend-aware synthesis optimization methodology wherein LLMs analyze actual post-layout timing, power, and area metrics from OpenLane results to iteratively refine synthesis TCL scripts, establishing a closed-loop optimization system that bridges the traditional gap between synthesis estimates and physical implementation reality. In contrast to conventional flows that rely on wire-load models, this methodology leverages real backend performance data to guide synthesis parameter tuning, optimization sequence selection, and constraint refinement, with the LLM functioning as an intelligent design space exploration agent. Experimental evaluation on representative digital designs demonstrates 15-30% improvements in timing closure and 10-20% area reduction compared to default synthesis flows, establishing MCP4EDA as the first practical LLM-controlled end-to-end open-source EDA automation system. The code and demo are avaiable at: http://www.agent4eda.com/

Key facts. Cited by 9 papers in the map (data through 14 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 16 of its 27 references that are in the map. First posted on arXiv 25 Jul 2025.

Builds on

16 of 27 references.

Closest ancestors · 1

Same direction, newest first

  1. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDA20 Aug

Other references · 15

  1. 2025Model Context Protocol (MCP): Landscape, Security Threats, and Future Research Directionscited by 265
  2. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  3. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  4. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  5. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  6. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  7. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  8. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
  9. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
  10. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  11. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 31
  12. 2025SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoningcited by 16
3 more
  1. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  2. 2022FlowTune: End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Banditcited by 11
  3. 2024Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placementcited by 2

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 3; 2026: 6.

9 papers.

Similar, not cited

Close in wording, no citation either way

  1. 2026Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
  2. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  3. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
  4. 2024EDA-Aware RTL Generation with Large Language Models
  5. 2024New Solutions on LLM Acceleration, Optimization, and Application
  6. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generation
  7. 2026SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization
  8. 2026LLM for EDA in Front-End Design: Challenges and Opportunities