Developing Synthesis Flows Without Human Knowledge
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Abstract (arXiv)
Design flows are the explicit combinations of design transformations, primarily involved in synthesis, placement and routing processes, to accomplish the design of Integrated Circuits (ICs) and System-on-Chip (SoC). Mostly, the flows are developed based on the knowledge of the experts. However, due to the large search space of design flows and the increasing design complexity, developing Intellectual Property (IP)-specific synthesis flows providing high Quality of Result (QoR) is extremely challenging. This work presents a fully autonomous framework that artificially produces design-specific synthesis flows without human guidance and baseline flows, using Convolutional Neural Network (CNN). The demonstrations are made by successfully designing logic synthesis flows of three large scaled designs.
Key facts. Cited by 29 papers in the map (data through 7 Oct 2026). First posted on arXiv 16 Apr 2018.
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Citing papers per year: 2021: 4; 2022: 6; 2023: 7; 2024: 8; 2025: 2; 2026: 2.
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- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
- 2021Machine Learning for Electronic Design Automation: A Surveycited by 71
- 2021A Survey of Machine Learning for Computer Architecture and Systemscited by 53
- 2021OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesiscited by 30
- 2021BOiLS: Bayesian Optimisation for Logic Synthesiscited by 18
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2022LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Modelscited by 7
- 2023RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUscited by 7
- 2024Differentiable Combinatorial Scheduling at Scalecited by 6
- 2026Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABCcited by 6
- 2024Circuit Transformer: A Transformer That Preserves Logical Equivalencecited by 5
- 2023AISYN: AI-driven Reinforcement Learning-Based Logic Synthesis Frameworkcited by 4
17 more
- 2023Accelerating Exact Combinatorial Optimization via RL-based Initialization -- A Case Study in Schedulingcited by 4
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designscited by 4
- 2024MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuningcited by 4
- 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Searchcited by 3
- 2022Rethinking Reinforcement Learning based Logic Synthesiscited by 2
- 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulationcited by 2
- 2024ShortCircuit: AlphaZero-Driven Circuit Designcited by 2
- 2022Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesiscited by 1
- 2022A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automationcited by 1
- 2022The prediction of the quality of results in Logic Synthesis using Transformer and Graph Neural Networkscited by 1
- 2023Towards the Imagenets of ML4EDAcited by 1
- 2024A Benchmark on Directed Graph Representation Learning in Hardware Designscited by 1
- 2025Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematicscited by 1
- 2022The Dark Side: Security Concerns in Machine Learning for EDAcited by 0
- 2024On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbationscited by 0
- 2025ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoringcited by 0
- 2026SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimizationcited by 0
- 2026SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization13 Aug 2026
- 2026Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC16 Apr 2026
- 2025ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring11 Aug 2025
- 2025Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics12 Jun 2025
- 2024A Benchmark on Directed Graph Representation Learning in Hardware Designs9 Oct 2024
- 2024ShortCircuit: AlphaZero-Driven Circuit Design19 Aug 2024
- 2024MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning25 Jul 2024
- 2024Differentiable Combinatorial Scheduling at Scale6 Jun 2024
- 2024Circuit Transformer: A Transformer That Preserves Logical Equivalence14 Mar 2024
- 2024On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations29 Feb 2024
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization22 Jan 2024
- 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation19 Jan 2024
17 more
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs9 Nov 2023
- 2023Towards the Imagenets of ML4EDA16 Oct 2023
- 2023Accelerating Exact Combinatorial Optimization via RL-based Initialization -- A Case Study in Scheduling19 Aug 2023
- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Design22 May 2023
- 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search22 May 2023
- 2023RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUs10 Apr 2023
- 2023AISYN: AI-driven Reinforcement Learning-Based Logic Synthesis Framework8 Feb 2023
- 2022The prediction of the quality of results in Logic Synthesis using Transformer and Graph Neural Networks23 Jul 2022
- 2022Rethinking Reinforcement Learning based Logic Synthesis16 May 2022
- 2022A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation19 Apr 2022
- 2022Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis5 Apr 2022
- 2022The Dark Side: Security Concerns in Machine Learning for EDA20 Mar 2022
- 2022LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models20 Jan 2022
- 2021BOiLS: Bayesian Optimisation for Logic Synthesis11 Nov 2021
- 2021OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis21 Oct 2021
- 2021A Survey of Machine Learning for Computer Architecture and Systems16 Feb 2021
- 2021Machine Learning for Electronic Design Automation: A Survey10 Jan 2021
- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 136
- 2021Machine Learning for Electronic Design Automation: A Surveycited by 71
- 2021A Survey of Machine Learning for Computer Architecture and Systemscited by 53
- 2021OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesiscited by 30
- 2021BOiLS: Bayesian Optimisation for Logic Synthesiscited by 18
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2022LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Modelscited by 7
- 2023RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUscited by 7
- 2024Differentiable Combinatorial Scheduling at Scalecited by 6
- 2024Circuit Transformer: A Transformer That Preserves Logical Equivalencecited by 5
- 2023AISYN: AI-driven Reinforcement Learning-Based Logic Synthesis Frameworkcited by 4
- 2023Accelerating Exact Combinatorial Optimization via RL-based Initialization -- A Case Study in Schedulingcited by 4
12 most cited of 27 All 27 (JSON)
- 2025ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring11 Aug 2025
- 2025Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics12 Jun 2025
- 2024A Benchmark on Directed Graph Representation Learning in Hardware Designs9 Oct 2024
- 2024ShortCircuit: AlphaZero-Driven Circuit Design19 Aug 2024
- 2024MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning25 Jul 2024
- 2024Differentiable Combinatorial Scheduling at Scale6 Jun 2024
- 2024Circuit Transformer: A Transformer That Preserves Logical Equivalence14 Mar 2024
- 2024On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations29 Feb 2024
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization22 Jan 2024
- 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation19 Jan 2024
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs9 Nov 2023
- 2023Towards the Imagenets of ML4EDA16 Oct 2023
12 newest of 27 All 27 (JSON)