mlsanityData to 14 Oct 2026

DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis

arXiv 2502.18297 ↗First posted 25 Feb 2025cs.LG cs.PLcited by 21

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Abstract (arXiv)

This paper introduces DeepCircuitX, a comprehensive repository-level dataset designed to advance RTL (Register Transfer Level) code understanding, generation, and power-performance-area (PPA) analysis. Unlike existing datasets that are limited to either file-level RTL code or physical layout data, DeepCircuitX provides a holistic, multilevel resource that spans repository, file, module, and block-level RTL code. This structure enables more nuanced training and evaluation of large language models (LLMs) for RTL-specific tasks. DeepCircuitX is enriched with Chain of Thought (CoT) annotations, offering detailed descriptions of functionality and structure at multiple levels. These annotations enhance its utility for a wide range of tasks, including RTL code understanding, generation, and completion. Additionally, the dataset includes synthesized netlists and PPA metrics, facilitating early-stage design exploration and enabling accurate PPA prediction directly from RTL code. We demonstrate the dataset's effectiveness on various LLMs finetuned with our dataset and confirm the quality with human evaluations. Our results highlight DeepCircuitX as a critical resource for advancing RTL-focused machine learning applications in hardware design automation.Our data is available at https://zeju.gitbook.io/lcm-team.

Key facts. Cited by 21 papers in the map (data through 14 Oct 2026). Builds on 27 of its 46 references that are in the map. First posted on arXiv 25 Feb 2025.

Builds on

27 of 46 references.

References · 27

  1. 2023GPT-4 Technical Reportcited by 18,396
  2. 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,459
  3. 2023Code Llama: Open Foundation Models for Codecited by 2,139
  4. 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,181
  5. 2024DeepSeek-V2: A Strong, Economical, and Efficient Mixture-of-Experts Language Modelcited by 1,135
  6. 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 885
  7. 2023CodeT5+: Open Code Large Language Models for Code Understanding and Generationcited by 333
  8. 2024DeepSeek-Coder-V2: Breaking the Barrier of Closed-Source Models in Code Intelligencecited by 331
  9. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  10. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  11. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  12. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
15 more
  1. 2021Machine Learning for Electronic Design Automation: A Surveycited by 72
  2. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  3. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  4. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  5. 2021DeepGate: Learning Neural Representations of Logic Gatescited by 37
  6. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  7. 2023DeepGate2: Functionality-Aware Circuit Representation Learningcited by 33
  8. 2024RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projectscited by 26
  9. 2024DeepGate3: Towards Scalable Circuit Representation Learningcited by 26
  10. 2025DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Modelcited by 23
  11. 2023MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Designcited by 19
  12. 2024EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROADcited by 13
  13. 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
  14. 2022CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)cited by 11
  15. 2023DeepSeq: Deep Sequential Circuit Learningcited by 7

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 8; 2026: 13.

21 papers.

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  1. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 13
  2. 2025DeepRTL2: A Versatile Model for RTL-Related Taskscited by 10
  3. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  4. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  5. 2026AlignCoder: Aligning Retrieval with Target Intent for Repository-Level Code Completioncited by 7
  6. 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
  7. 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generationcited by 4
  8. 2026DRAINCODE: Stealthy Energy Consumption Attacks on Retrieval-Augmented Code Generation via Context Poisoningcited by 3
  9. 2026CktEvo: Repository-Level RTL Code Benchmark for Design Evolutioncited by 3
  10. 2026QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesiscited by 2
  11. 2026PhoenixRepair: Rethinking Repair Strategy Exploration in Software Agentscited by 2
  12. 2025ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesiscited by 1
9 more
  1. 2025Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learningcited by 1
  2. 2026TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilogcited by 1
  3. 2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Modelscited by 1
  4. 2025TRACE: Learning to Compute on Circuit Graphscited by 0
  5. 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mappingcited by 0
  6. 2026RTLocating: Intent-aware RTL Localization for Hardware Design Iterationcited by 0
  7. 2026Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automationcited by 0
  8. 2026UniRTL: Unifying Code and Graph for Robust RTL Representation Learningcited by 0
  9. 2026PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devicescited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2025RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation
  2. 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
  3. 2025Understanding and Mitigating Errors of LLM-Generated RTL Code
  4. 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs
  5. 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
  6. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  7. 2024EDA-Aware RTL Generation with Large Language Models
  8. 2025RTLSquad: Multi-Agent Based Interpretable RTL Design