Fixing Hardware Security Bugs with Large Language Models
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Abstract (arXiv)
Novel AI-based code-writing Large Language Models (LLMs) such as OpenAI's Codex have demonstrated capabilities in many coding-adjacent domains. In this work we consider how LLMs maybe leveraged to automatically repair security relevant bugs present in hardware designs. We focus on bug repair in code written in the Hardware Description Language Verilog. For this study we build a corpus of domain-representative hardware security bugs. We then design and implement a framework to quantitatively evaluate the performance of any LLM tasked with fixing the specified bugs. The framework supports design space exploration of prompts (i.e., prompt engineering) and identifying the best parameters for the LLM. We show that an ensemble of LLMs can repair all ten of our benchmarks. This ensemble outperforms the state-of-the-art Cirfix hardware bug repair tool on its own suite of bugs. These results show that LLMs can repair hardware security bugs and the framework is an important step towards the ultimate goal of an automated end-to-end bug repair framework.
Key facts. Cited by 24 papers in the map (data through 7 Oct 2026). First posted on arXiv 2 Feb 2023.
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Citing papers per year: 2023: 6; 2024: 6; 2025: 8; 2026: 4.
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- 2023A Survey on Large Language Model (LLM) Security and Privacy: The Good, the Bad, and the Uglycited by 380
- 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2023Fully Autonomous Programming with Large Language Modelscited by 31
- 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
- 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
- 2024Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledgecited by 10
- 2024Compiler generated feedback for Large Language Modelscited by 9
- 2025Large Language Models for Security Operations Centers: A Comprehensive Surveycited by 9
- 2023FLAG: Finding Line Anomalies (in code) with Generative AIcited by 7
- 2023ZeroLeak: Using LLMs for Scalable and Cost Effective Side-Channel Patchingcited by 6
- 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Modelscited by 5
12 more
- 2025Towards LLM-based Root Cause Analysis of Hardware Design Failurescited by 4
- 2024LLM-aided explanations of EDA synthesis errorscited by 3
- 2025PerfCoder: Large Language Models for Interpretable Code Performance Optimizationcited by 3
- 2026EvoRepair: Enhancing Vulnerability Repair Agents Through Experience-Based Self-Evolutioncited by 2
- 2024Digital ASIC Design with Ongoing LLMs: Strategies and Prospectscited by 1
- 2025HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databasescited by 1
- 2025Empirical evaluation of LLMs in predicting fixes of Configuration bugs in Smart Home Systemcited by 0
- 2025Large Language Models in Cybersecurity: Applications, Vulnerabilities, and Defense Techniquescited by 0
- 2025Software Vulnerability Management in the Era of Artificial Intelligence: An Industry Perspectivecited by 0
- 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detectioncited by 0
- 2026EstRTL: Functional Estimation Guided RTL Code Generationcited by 0
- 2026VeriPilot: An LLM-Powered Verilog Debugging Frameworkcited by 0
- 2026VeriPilot: An LLM-Powered Verilog Debugging Framework22 Jun 2026
- 2026EstRTL: Functional Estimation Guided RTL Code Generation1 Jun 2026
- 2026EvoRepair: Enhancing Vulnerability Repair Agents Through Experience-Based Self-Evolution28 May 2026
- 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection5 Mar 2026
- 2025Software Vulnerability Management in the Era of Artificial Intelligence: An Industry Perspective20 Dec 2025
- 2025PerfCoder: Large Language Models for Interpretable Code Performance Optimization16 Dec 2025
- 2025Large Language Models for Security Operations Centers: A Comprehensive Survey13 Sep 2025
- 2025Large Language Models in Cybersecurity: Applications, Vulnerabilities, and Defense Techniques18 Jul 2025
- 2025Towards LLM-based Root Cause Analysis of Hardware Design Failures9 Jul 2025
- 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models25 Jun 2025
- 2025HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databases21 May 2025
- 2025Empirical evaluation of LLMs in predicting fixes of Configuration bugs in Smart Home System16 Feb 2025
12 more
- 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust11 May 2024
- 2024Digital ASIC Design with Ongoing LLMs: Strategies and Prospects25 Apr 2024
- 2024LLM-aided explanations of EDA synthesis errors7 Apr 2024
- 2024Compiler generated feedback for Large Language Models18 Mar 2024
- 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debugging28 Jan 2024
- 2024Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge27 Jan 2024
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation28 Dec 2023
- 2023A Survey on Large Language Model (LLM) Security and Privacy: The Good, the Bad, and the Ugly4 Dec 2023
- 2023ZeroLeak: Using LLMs for Scalable and Cost Effective Side-Channel Patching24 Aug 2023
- 2023VeriGen: A Large Language Model for Verilog Code Generation28 Jul 2023
- 2023FLAG: Finding Line Anomalies (in code) with Generative AI22 Jun 2023
- 2023Fully Autonomous Programming with Large Language Models20 Apr 2023
- 2023A Survey on Large Language Model (LLM) Security and Privacy: The Good, the Bad, and the Uglycited by 380
- 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2023Fully Autonomous Programming with Large Language Modelscited by 31
- 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
- 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
- 2024Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledgecited by 10
- 2024Compiler generated feedback for Large Language Modelscited by 9
- 2025Large Language Models for Security Operations Centers: A Comprehensive Surveycited by 9
- 2023FLAG: Finding Line Anomalies (in code) with Generative AIcited by 7
- 2023ZeroLeak: Using LLMs for Scalable and Cost Effective Side-Channel Patchingcited by 6
- 2025Towards LLM-based Root Cause Analysis of Hardware Design Failurescited by 4
12 most cited of 20 All 20 (JSON)
- 2026VeriPilot: An LLM-Powered Verilog Debugging Framework22 Jun 2026
- 2026EstRTL: Functional Estimation Guided RTL Code Generation1 Jun 2026
- 2025Software Vulnerability Management in the Era of Artificial Intelligence: An Industry Perspective20 Dec 2025
- 2025PerfCoder: Large Language Models for Interpretable Code Performance Optimization16 Dec 2025
- 2025Large Language Models for Security Operations Centers: A Comprehensive Survey13 Sep 2025
- 2025Large Language Models in Cybersecurity: Applications, Vulnerabilities, and Defense Techniques18 Jul 2025
- 2025Towards LLM-based Root Cause Analysis of Hardware Design Failures9 Jul 2025
- 2025Empirical evaluation of LLMs in predicting fixes of Configuration bugs in Smart Home System16 Feb 2025
- 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust11 May 2024
- 2024Digital ASIC Design with Ongoing LLMs: Strategies and Prospects25 Apr 2024
- 2024LLM-aided explanations of EDA synthesis errors7 Apr 2024
- 2024Compiler generated feedback for Large Language Models18 Mar 2024
12 newest of 20 All 20 (JSON)