mlsanityData to 7 Oct 2026

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

arXiv 2408.08927 ↗First posted 15 Aug 2024cs.AI cs.CLcited by 85

On the map: LLM agents and tool use → Software engineering coding agents

Abstract (arXiv)

Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using collaborative Verilog tools (i.e., syntax checker, simulator, and waveform tracer). Firstly, we propose a task planner that utilizes a novel Task and Circuit Relation Graph retrieval method to construct a holistic plan based on module descriptions. To debug and fix functional errors, we develop a novel and efficient abstract syntax tree (AST)-based waveform tracing tool, which is integrated within the autonomous Verilog completion flow. The proposed methodology successfully generates 94.2% syntactically and functionally correct Verilog code, surpassing the state-of-the-art methods by 33.9% on the VerilogEval-Human v2 benchmark.

Key facts. Cited by 85 papers in the map (data through 7 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 11 of its 22 references that are in the map. First posted on arXiv 15 Aug 2024.

Builds on

11 of 22 references.

Closest ancestors · 1

Same direction, newest first

  1. 2024SWE-agent: Agent-Computer Interfaces Enable Automated Software Engineering6 May

Other references · 10

  1. 2022ReAct: Synergizing Reasoning and Acting in Language Modelscited by 8,355
  2. 2023A Survey on Large Language Model based Autonomous Agentscited by 2,203
  3. 2024From Local to Global: A Graph RAG Approach to Query-Focused Summarizationcited by 1,411
  4. 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,154
  5. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  6. 2023CodePlan: Repository-level Coding using LLMs and Planningcited by 139
  7. 2023CodeGen2: Lessons for Training LLMs on Programming and Natural Languagescited by 124
  8. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
  9. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 69
  10. 2023CodeTF: One-stop Transformer Library for State-of-the-art Code LLMscited by 21

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2024: 7; 2025: 36; 2026: 42.

85 papers.

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  1. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  2. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 41
  3. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  4. 2025Large Language Models for Planning: A Comprehensive and Systematic Surveycited by 38
  5. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generationcited by 31
  6. 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
  7. 2025VFlow: Discovering Optimal Agentic Workflows for Verilog Generationcited by 19
  8. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15
  9. 2024DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agentcited by 15
  10. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  11. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  12. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
38 more
  1. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMscited by 12
  2. 2026MemPO: Self-Memory Policy Optimization for Long-Horizon Agentscited by 11
  3. 2024CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generationcited by 9
  4. 2025QAgent: An LLM-based Multi-Agent System for Autonomous OpenQASM programmingcited by 9
  5. 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
  6. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  7. 2025LLM-DSE: Searching Accelerator Parameters with LLM Agentscited by 7
  8. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  9. 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
  10. 2026ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Designcited by 7
  11. 2024Does Few-Shot Learning Help LLM Performance in Code Synthesis?cited by 6
  12. 2026Agentic Hardware Design as Repository-Level Code Evolutioncited by 6
  13. 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflectioncited by 5
  14. 2025ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learningcited by 5
  15. 2025LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Modelscited by 5
  16. 2025Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automationcited by 4
  17. 2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Modelscited by 4
  18. 2025VFocus: Better Verilog Generation from Large Language Model via Focused Reasoningcited by 4
  19. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generationcited by 4
  20. 2026LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generationcited by 4
  21. 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generationcited by 4
  22. 2026VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generationcited by 4
  23. 2025TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generationcited by 3
  24. 2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generationcited by 3
  25. 2026COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generationcited by 3
  26. 2026Trace2Skill: Verifier-Guided Skill Evolution for Long-Context EDA Agentscited by 3
  27. 2025Symmetrization Weighted Binary Cross-Entropy: Modeling Perceptual Asymmetry for Human-Consistent Neural Edge Detectioncited by 2
  28. 2025Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graphcited by 2
  29. 2025hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generationcited by 2
  30. 2025SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chipcited by 2
  31. 2025ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluationcited by 2
  32. 2025GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identificationcited by 2
  33. 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimizationcited by 2
  34. 2026LLM-Based Multi-Agent Systems for Code Generation: A Multi-Vocal Literature Reviewcited by 2
  35. 2026RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revisioncited by 2
  36. 2025Polymath: A Self-Optimizing Agent with Dynamic Hierarchical Workflowcited by 1
  37. 2025CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systemscited by 1
  38. 2025The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generationcited by 1

50 most cited of 85 All 85 (JSON)

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  1. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
  2. 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
  3. 2026VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
  4. 2025EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
  5. 2026Exploring the Agentic Frontier of Verilog Code Generation
  6. 2026From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation
  7. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs
  8. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs