mlsanityData to 14 Oct 2026

EstRTL: Functional Estimation Guided RTL Code Generation

arXiv 2606.09867 ↗First posted 1 Jun 2026cs.AR cs.AIcited by 0

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Abstract (arXiv)

Optimizing register transfer level (RTL) code is of vital importance in hardware design. Large language models (LLMs) provide new methods for the automatic generation and optimization of RTL code, offering the potential to significantly accelerate the design process and reduce human effort. However, existing methods for generating RTL code often focus on model fine-tuning and the use of various expansion techniques to enhance the RTL code generation capabilities, lacking attention to the functional correctness. Ensuring that the generated RTL code not only compiles successfully but also behaves as intended in real hardware implementations remains a critical challenge. To address this issue, we propose EstRTL, an LLM-powered collaborative agent framework for RTL code generation based on static functional score estimation. EstRTL operates a three-stage paradigm: Generation, Estimation and Correction. During the stages, the functional estimation agent statically evaluates the generated code based on score and assessment results, and decides whether to output the code directly, return it for regeneration, or forward it to the code correction agent. This framework can be applied to various LLMs that designed for RTL code generation, further enhancing the correctness of the generated code. By providing quantitative scores and human-readable requirements comparisons, it improves the transparency of AI-assisted RTL code generation. Experiments show that EstRTL significantly improves the correctness of RTL code generation by generic LLM by 3.2%-9.0%, demonstrating the practical value of our system. The codes and experimental results are open-sourced at link: https://anonymous.4open.science/status/EstRTL-E200/.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 29 of its 40 references that are in the map. First posted on arXiv 1 Jun 2026.

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29 of 40 references.

References · 29

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  9. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  10. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  11. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 41
  12. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
17 more
  1. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  2. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  3. 2023L2MAC: Large Language Model Automatic Computer for Extensive Code Generationcited by 30
  4. 2023Fixing Hardware Security Bugs with Large Language Modelscited by 24
  5. 2024CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Designcited by 24
  6. 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
  7. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
  8. 2025Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systemscited by 18
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  10. 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 13
  11. 2024ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generationcited by 9
  12. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
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  14. 2025Automatic Question & Answer Generation Using Generative Large Language Model (LLM)cited by 4
  15. 2025Bridging LLM-Generated Code and Requirements: Reverse Generation technique and SBC Metric for Developer Insightscited by 3
  16. 2016Unifying Requirements and Code: an Examplecited by 1
  17. 2019A Feature Based Methodology for Variable Requirements Reverse Engineeringcited by 1

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