mlsanityData to 14 Oct 2026

Hardware Design and Security in the Era of Chiplets and LLMs

arXiv 2608.05063 ↗First posted 5 Aug 2026cs.CR cs.AI cs.ARcited by 0

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Abstract (arXiv)

The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield, modularity, design productivity, etc., they radically expand the hardware attack surface. This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems (including hardware stacks for LLM acceleration) across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines. To secure chiplet systems, we review a powerful defense approach that leverages 2.5D split manufacturing and active interposers for physically isolated Root of Trust (RoT) architectures. To secure LLM-driven EDA pipelines, we first identify native threats and then review state-of-the-art defense techniques. Finally, we discuss how LLM systems can advance hardware security efforts for modern systems, including chiplets.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 44 of its 74 references that are in the map. First posted on arXiv 5 Aug 2026.

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44 of 74 references.

References · 44

  1. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  2. 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 43
  3. 2023(Security) Assertions by Large Language Modelscited by 32
  4. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 20
  5. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 19
  6. 2024Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLMcited by 18
  7. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
  8. 2024LLM-Aided Testbench Generation and Bug Detection for Finite-State Machinescited by 17
  9. 2024C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gapcited by 16
  10. 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 15
  11. 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
  12. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
32 more
  1. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
  2. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
  3. 2025NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestrationcited by 9
  4. 2025I Know What You Said: Unveiling Hardware Cache Side-Channels in Local Large Language Model Inferencecited by 7
  5. 2025Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Formcited by 7
  6. 2025Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVAcited by 6
  7. 2025MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Modelscited by 5
  8. 2025LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMscited by 5
  9. 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimizationcited by 5
  10. 2023Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Modelscited by 4
  11. 2025LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugscited by 4
  12. 2026Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modescited by 4
  13. 20202.5D Root of Trust: Secure System-Level Integration of Untrusted Chipletscited by 3
  14. 2025Large Language Models (LLMs) for Electronic Design Automation (EDA)cited by 3
  15. 2025Can Transformer Memory Be Corrupted? Investigating Cache-Side Vulnerabilities in Large Language Modelscited by 3
  16. 2025CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakagecited by 3
  17. 2025CHIME: Chiplet-based Heterogeneous Near-Memory Acceleration for Edge Multimodal LLM Inferencecited by 3
  18. 2026Semantic Consensus Decoding: Backdoor Defense for Verilog Code Generationcited by 3
  19. 2026Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protectioncited by 3
  20. 2026HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarkingcited by 3
  21. 2026Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verificationcited by 3
  22. 2025ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redactioncited by 2
  23. 2026TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertioncited by 2
  24. 2026LLM4PQC - Accurate and Efficient Synthesis of PQC Cores by Feedback-Driven LLMscited by 2
  25. 2026VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilogcited by 2
  26. 2026From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Designcited by 2
  27. 2026SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generationcited by 2
  28. 2018Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturingcited by 1
  29. 20193D Integration: Another Dimension Toward Hardware Securitycited by 1
  30. 2019A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnectscited by 1
  31. 2022Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systemscited by 1
  32. 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1

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