LEGO: An LLM Skill-Based Front-End Design Generation Platform

arXiv 2604.23355 ↗First posted 25 Apr 2026cs.AIcited by 0

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Abstract (arXiv)

Existing LLM-based EDA agents are often isolated task-specific systems. This leads to repeated engineering effort and limited reuse of successful design and debugging strategies. We present LEGO, a unified skill-based platform for front-end design generation. It decomposes the digital front-end flow into six independent steps and represents every agent capability as a standardized composable circuit skill within a plug-and-play architecture. To build this skill library, we survey more than 100 papers, select 11 representative open-source projects, and extract 42 executable circuit skills within a six-step finite state machine formulation. Circuit Skill Builder automates skill extraction with linear scalability. Agent Skill RAG achieves submillisecond retrieval without relying on embedding models. Empirical evaluation on a hard subset of 41 VerilogEval v2 problems that gpt-5.2-codex fails to solve under extra-high reasoning effort shows that individual circuit skills constructed within LEGO raise Pass@1 from 0.000 to 0.805. This is an 80.5% gain over the baseline. Cross-project skill compositions also reach 0.805 Pass@1. They outperform hierarchy-verilog by 14.6% and VerilogCoder by 2.5%. They also match MAGE. These results show that modular skill composition supports both effective and flexible RTL design automation. The LEGO platform and all circuit skills are publicly available at GitHub: https://github.com/loujc/LEGO-An-LLM-Skill-Based-Front-End-Design-Generation-Platform

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 19 of its 29 references that are in the map. First posted on arXiv 25 Apr 2026.

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References · 19

2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 80
2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 38
2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
2025OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generationcited by 30

7 more

2025Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systemscited by 17
2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metriccited by 12
2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 8
2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
2024HDL-GPT: High-Quality HDL is All You Needcited by 1
2025BRIDGES: Bridging Graph Modality and Large Language Models within EDA Taskscited by 1

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