CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization
On the map: LLM agents and tool use → Software engineering coding agents
Abstract (arXiv)
Optimizing Register Transfer Level (RTL) code is a critical step in Electronic Design Automation (EDA) for improving power, performance, and area (PPA). We present CODMAS (Collaborative Optimization via a Dialectic Multi-Agent System), a framework that combines structured dialectic reasoning with domain-aware code generation and deterministic evaluation to automate RTL optimization. At the core of CODMAS are two dialectic agents: the Articulator, inspired by rubber-duck debugging, which articulates stepwise transformation plans and exposes latent assumptions; and the Hypothesis Partner, which predicts outcomes and reconciles deviations between expected and actual behavior to guide targeted refinements. These agents direct a Domain-Specific Coding Agent (DCA) to generate architecture-aware Verilog edits and a Code Evaluation Agent (CEA) to verify syntax, functionality, and PPA metrics. We introduce RTLOPT, a benchmark of 120 Verilog triples (unoptimized, optimized, testbench) for pipelining and clock-gating transformations. Across proprietary and open LLMs, CODMAS achieves ~25% reduction in critical path delay for pipelining and ~22% power reduction for clock gating, while reducing functional and compilation failures compared to strong prompting and agentic baselines. These results demonstrate that structured multi-agent reasoning can significantly enhance automated RTL optimization and scale to more complex designs and broader optimization tasks.
Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 17 of its 24 references that are in the map. First posted on arXiv 17 Mar 2026.
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17 of 24 references.
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Other references · 16
- 2022ReAct: Synergizing Reasoning and Acting in Language Modelscited by 8,695
- 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
- 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
- 2024Granite Code Models: A Family of Open Foundation Models for Code Intelligencecited by 117
- 2023ChipGPT: How far are we from natural language hardware designcited by 105
- 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
- 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
- 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 43
- 2023ChiPFormer: Transferable Chip Placement via Offline Decision Transformercited by 42
- 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 31
- 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
- 2025Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systemscited by 18
4 more
- 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 15
- 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
- 2024All Artificial, Less Intelligence: GenAI through the Lens of Formal Verificationcited by 11
- 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 9
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Citing papers per year: 2026: 2.
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- 2025Automated Multi-Agent Workflows for RTL Design
- 2026VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generation
- 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
- 2025RTLSquad: Multi-Agent Based Interpretable RTL Design
- 2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
- 2025PEFA-AI: Advancing Open-source LLMs for RTL generation using Progressive Error Feedback Agentic-AI
- 2026Can Agents Design Better Chips with a Higher Level Abstraction?
- 2026VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs