mlsanityData to 14 Oct 2026

HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL

arXiv 2503.16528 ↗First posted 18 Mar 2025cs.CL cs.AIcited by 17

On the map: Retrieval-augmented generation → RAG for code

Abstract (arXiv)

Recent advances in large language models (LLMs) have demonstrated remarkable capabilities in code generation tasks. However, when applied to hardware description languages (HDL), these models exhibit significant limitations due to data scarcity, resulting in hallucinations and incorrect code generation. To address these challenges, we propose HDLCoRe, a training-free framework that enhances LLMs' HDL generation capabilities through prompt engineering techniques and retrieval-augmented generation (RAG). Our approach consists of two main components: (1) an HDL-aware Chain-of-Thought (CoT) prompting technique with self-verification that classifies tasks by complexity and type, incorporates domain-specific knowledge, and guides LLMs through step-by-step self-simulation for error correction; and (2) a two-stage heterogeneous RAG system that addresses formatting inconsistencies through key component extraction and efficiently retrieves relevant HDL examples through sequential filtering and re-ranking. HDLCoRe eliminates the need for model fine-tuning while substantially improving LLMs' HDL generation capabilities. Experimental results demonstrate that our framework achieves superior performance on the RTLLM2.0 benchmark, significantly reducing hallucinations and improving both syntactic and functional correctness.

Key facts. Cited by 17 papers in the map (data through 14 Oct 2026). Placed in RAG for code, one of 15 directions in Retrieval-augmented generation. Builds on 31 of its 44 references that are in the map. First posted on arXiv 18 Mar 2025.

Builds on

31 of 44 references.

References · 31

  1. 2020Language Models are Few-Shot Learnerscited by 32,419
  2. 2023GPT-4 Technical Reportcited by 18,396
  3. 2023LLaMA: Open and Efficient Foundation Language Modelscited by 14,132
  4. 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,459
  5. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  6. 2023Qwen Technical Reportcited by 3,344
  7. 2021Improving language models by retrieving from trillions of tokenscited by 1,293
  8. 2023Survey on Factuality in Large Language Models: Knowledge, Retrieval and Domain-Specificitycited by 206
  9. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
  10. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  11. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 148
  12. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
19 more
  1. 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 100
  2. 2023AutoChip: Automating HDL Generation Using LLM Feedbackcited by 83
  3. 2021Machine Learning for Electronic Design Automation: A Surveycited by 72
  4. 2023RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solutioncited by 71
  5. 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 61
  6. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  7. 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 46
  8. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  9. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  10. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  11. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMscited by 36
  12. 2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineerscited by 25
  13. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
  14. 2025VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistencycited by 11
  15. 2025ClimateLLM: Efficient Weather Forecasting via Frequency-Aware Large Language Modelscited by 9
  16. 2024LLMPirate: LLMs for Black-box Hardware IP Piracycited by 7
  17. 2025Paradigm-Based Automatic HDL Code Generation Using LLMscited by 6
  18. 2025Network-informed Prompt Engineering against Organized Astroturf Campaigns under Extreme Class Imbalancecited by 4
  19. 2024Classification-Based Automatic HDL Code Generation Using LLMscited by 3

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 7; 2026: 10.

17 papers.

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  1. 2025Learning to Deliberate: Meta-policy Collaboration for Agentic LLMs with Multi-agent Reinforcement Learningcited by 18
  2. 2026Auditing Multi-Agent LLM Reasoning Trees Outperforms Majority Vote and LLM-as-Judgecited by 18
  3. 2026TemporalBench: A Benchmark for Evaluating LLM-Based Agents on Contextual and Event-Informed Time Series Taskscited by 17
  4. 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
  5. 2025Maestro: Learning to Collaborate via Conditional Listwise Policy Optimization for Multi-Agent LLMscited by 14
  6. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  7. 2026Adaptive Collaboration with Humans: Metacognitive Policy Optimization for Multi-Agent LLMs with Continual Learningcited by 9
  8. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  9. 2025Structured Spectral Reasoning for Frequency-Adaptive Multimodal Recommendationcited by 6
  10. 2026RaMem: Contextual Reinstatement for Long-term Agentic Memorycited by 6
  11. 2026HardSecBench: Benchmarking the Security Awareness of LLMs for Hardware Code Generationcited by 5
  12. 2026Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generationcited by 2
5 more
  1. 2026De-conflating Preference and Qualification: Constrained Dual-Perspective Reasoning for Job Recommendation with Large Language Modelscited by 2
  2. 2025A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementationcited by 0
  3. 2026VLM4Rec: Multimodal Semantic Representation for Recommendation with Large Vision-Language Modelscited by 0
  4. 2026SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarizationcited by 0
  5. 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2025Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
  2. 2025CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference
  3. 2025hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation
  4. 2025SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
  5. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  6. 2024HDLdebugger: Streamlining HDL debugging with Large Language Models
  7. 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
  8. 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation