OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
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Abstract (arXiv)
OpenRTLSet introduces the largest fully open-source dataset for hardware design, offering over 131,000 diverse Verilog code samples to the research community and industry. Our dataset uniquely combines Verilog code from GitHub repositories (102k modules), VHDL translations (5k modules), and synthesizable C/C++ translations (24k modules), all freely accessible without proprietary restrictions. Using the reasoning model DeepSeek-R1, we generated paired natural language descriptions for each code sample, enabling fine-tuning of various language model families (e.g., Qwen and Granite) for Verilog code generation. Our dataset explores multiple options, including Verilator-generated C++ files as additional context during labeling, quantization techniques (INT4 vs. BF16), and performance differences across model sizes (7B-32B parameters). OpenRTLSet demonstrates that open-source approaches can achieve superior performance in hardware design tasks, establishing a new foundation for accessible research and commercial use in this domain.
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References · 22
- 2024Qwen2.5 Technical Reportcited by 4,713
- 2023Code Llama: Open Foundation Models for Codecited by 2,105
- 2024DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligencecited by 1,154
- 2024Qwen2.5-Coder Technical Reportcited by 1,151
- 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 246
- 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
- 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
- 2024BetterV: Controlled Verilog Generation with Discriminative Guidancecited by 99
- 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
- 2024MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generationcited by 45
- 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
- 2024PyBench: Evaluating LLM Agent on various real-world coding taskscited by 24
10 more
- 2021ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representationcited by 21
- 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
- 2024LLM-Aided Efficient Hardware Design Automationcited by 11
- 2023SteloCoder: a Decoder-Only LLM for Multi-Language to Python Code Translationcited by 9
- 2023HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesiscited by 9
- 2024Evaluating LLMs for Hardware Design and Testcited by 8
- 2024A Study of Vulnerability Repair in JavaScript Programs with Large Language Modelscited by 7
- 2024New Solutions on LLM Acceleration, Optimization, and Applicationcited by 7
- 2023Spade: An Expression-Based HDL With Pipelinescited by 1
- 2024Veryl: A New Hardware Description Language as an Altarnative to SystemVerilogcited by 1
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