LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
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Abstract (arXiv)
The integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) and hardware security is rapidly reshaping the semiconductor industry. While LLMs offer unprecedented capabilities in generating Register Transfer Level (RTL) code, automating testbenches, and bridging the semantic gap between high-level specifications and silicon, they simultaneously introduce severe vulnerabilities. This comprehensive review provides an in-depth analysis of the state-of-the-art in LLM-driven hardware design, organized around key advancements in EDA synthesis, hardware trust, design for security, and education. We systematically expand on the methodologies of recent breakthroughs -- from reasoning-driven synthesis and multi-agent vulnerability extraction to data contamination and adversarial machine learning (ML) evasion. We integrate general discussions on critical countermeasures, such as dynamic benchmarking to combat data memorization and aggressive red-teaming for robust security assessment. Finally, we synthesize cross-cutting lessons learned to guide future research toward secure, trustworthy, and autonomous design ecosystems.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 37 of its 49 references that are in the map. First posted on arXiv 11 May 2026.
Builds on
37 of 49 references.
References · 37
- 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
- 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 43
- 2023(Security) Assertions by Large Language Modelscited by 32
- 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 20
- 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 19
- 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
- 2024LLM-Aided Testbench Generation and Bug Detection for Finite-State Machinescited by 17
- 2024C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gapcited by 16
- 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 15
- 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
- 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
- 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
25 more
- 2025Towards Effective Offensive Security LLM Agents: Hyperparameter Tuning, LLM as a Judge, and a Lightweight CTF Benchmarkcited by 12
- 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
- 2025Can Reasoning Models Reason about Hardware? An Agentic HLS Perspectivecited by 9
- 2025NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestrationcited by 9
- 2025Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Formcited by 7
- 2024AttackGNN: Red-Teaming GNNs in Hardware Security Using Reinforcement Learningcited by 6
- 2025Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVAcited by 6
- 2025MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Modelscited by 5
- 2025LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMscited by 5
- 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimizationcited by 5
- 2025LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugscited by 4
- 2026Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modescited by 4
- 2025Large Language Models (LLMs) for Electronic Design Automation (EDA)cited by 3
- 2026Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protectioncited by 3
- 2026HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarkingcited by 3
- 2026Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verificationcited by 3
- 2025ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redactioncited by 2
- 2026TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertioncited by 2
- 2026LLM4PQC - Accurate and Efficient Synthesis of PQC Cores by Feedback-Driven LLMscited by 2
- 2026VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilogcited by 2
- 2026From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Designcited by 2
- 2026VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generationcited by 1
- 2026GUIDE: GenAI Units In Digital Design Educationcited by 1
- 2026AI In Cybersecurity Education -- Scalable Agentic CTF Design Principles and Educational Outcomescited by 1
- 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generationcited by 1
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Citing papers per year: 2026: 1.
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- 2026LLM for EDA in Front-End Design: Challenges and Opportunities
- 2026Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
- 2026A Survey on LLM-Integrated Hardware Design Verification
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
- 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- 2025LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation